CMOS SuperSync FIFO™
65,536 x 9
131,072 x 9
IDT72281
IDT72291
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
FEATURES:
• Choose among the following memory organizations:
IDT72281
IDT72291
65,536 x 9
131,072 x 9
• Pin-compatible with the IDT72261LA/72271LA SuperSync FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable
settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
DESCRIPTION:
TheIDT72281/72291areexceptionallydeep,highspeed,CMOSFirst-In-
First-Out(FIFO)memorieswithclockedreadandwritecontrols. TheseFIFOs
offernumerousimprovementsoverpreviousSuperSyncFIFOs,includingthe
following:
• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable
clock cycle counting delay associated with the latency period found on
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)
SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecom-
munications,datacommunicationsandotherapplicationsthatneedtobuffer
largeamountsofdata.
• Independent Read and Write clocks (permit reading and writing
simultaneously)
FUNCTIONALBLOCKDIAGRAM
D0 -D8
WEN
WCLK
LD
SEN
OFFSET REGISTER
INPUT REGISTER
FF/IR
PAF
EF/OR
PAE
FLAG
LOGIC
WRITE CONTROL
LOGIC
HF
FWFT/SI
RAM ARRAY
65,536 x 9
131,072 x 9
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
RT
OUTPUT REGISTER
MRS
PRS
RESET
LOGIC
RCLK
REN
Q0 -Q8
4675 drw01
OE
IDT, IDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MARCH 2013
1
©
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4675/5
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