IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTION
Symbol
D0–D8
MRS
Name
I/O
Description
DataInputs
I
I
Datainputsfora9-bitbus.
MasterReset
PartialReset
Retransmit
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of two program-
mableflagdefaultsettings,andserialorparallelprogrammingoftheoffsetsettings.
PRS
RT
I
I
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and
programmableflagsettingsareallretained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, program
ming method, existing timing mode or programmable flag settings. RT is useful to reread data from
the first physical location of the FIFO.
FWFT/SI
WCLK
FirstWordFall
Through/Serial In
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset,
thispinfunctionsasaserialinputforloadingoffsetregisters
WriteClock
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programming, and when enabled by SEN, the rising edge of
WCLKwritesonebitofdataintotheprogrammableregisterforserialprogramming.
WEN
RCLK
WriteEnable
ReadClock
I
I
WENenablesWCLKforwritingdataintotheFIFOmemoryandoffsetregisters.
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from
theprogrammableregisters.
REN
OE
SEN
LD
Read Enable
OutputEnable
SerialEnable
Load
I
I
I
I
REN enablesRCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.
OEcontrolstheoutputimpedanceofQn.
SENenablesserialloadingofprogrammableflagoffsets.
During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023 and determines
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to
andreadingfromtheoffsetregisters.
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master Reset.
FF/IR
Full Flag/
Input Ready
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO
memory is full. In the FWFT mode, the IRfunction is selected. IR indicates whether or not there is
spaceavailableforwritingtotheFIFOmemory.
EF/OR
PAF
EmptyFlag/
OutputReady
O
O
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO
memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there
isvaliddataavailableattheoutputs.
Programmable
Almost-FullFlag
PAF goes LOW if the number of words in the FIFO memory is more than total word capacity of the
FIFOminusthefulloffsetvaluem, whichisstoredintheFullOffsetregister. Therearetwopossible
default values for m: 127 or 1,023.
PAE
Programmable
Almost-EmptyFlag
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in
the Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values
for n can be programmed into the device.
HF
Q0–Q8
VCC
Half-FullFlag
DataOutputs
Power
O
O
HF indicateswhethertheFIFOmemoryismoreorlessthanhalf-full.
Dataoutputsfora9-bus
+5 Volt power supply pins.
GND
Ground
Groundpins.
4
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