Datasheet > 72291L15PF

72291L15PF

更新时间： 2023-01-03 02:12:43

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
26页	418K
描述
TQFP-64, Tray

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数据手册

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72291L15PF 数据手册

IDT72281/72291

CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault

settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023

withserialprogramming. Theflagsareupdatedaccordingtothetimingmode

anddefaultoffsetsselected.

DESCRIPTION(CONTINUED)

FWFTmode. HF,PAEandPAFarealwaysavailableforuse,irrespectiveof

timingmode.

The Partial Reset (PRS) also sets the read and write pointers to the first

locationofthememory. However,thetimingmode,partialflagprogramming

method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset

remainunchanged.Theflagsareupdatedaccordingtothetimingmodeand

offsets in effect. PRS is useful for resetting a device in mid-operation, when

reprogrammingpartialflagswouldbeundesirable.

TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan

once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit

operationbysettingthereadpointertothefirstlocationofthememoryarray.

If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill

automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply

currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol

inputs)willimmediatelytakethedeviceoutofthepowerdownstate.

The IDT72281/72291 are fabricated using high speed submicron CMOS

technology.

PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin

memory. (SeeTableIandTableII.) Programmableoffsetsdeterminetheflag

switchingthresholdandcanbeloadedbytwomethods:parallelorserial. Two

defaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchat127

or1,023locationsfromtheemptyboundaryandthePAFthresholdcanbeset

at127or1,023locationsfromthefullboundary. Thesechoicesaremadewith

the LD pin during Master Reset.

For serialprogramming,SENtogetherwithLDoneachrisingedgeofWCLK,

are used to load the offset registers via the Serial Input (SI). For parallel

programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused

toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge

ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether

serialorparalleloffsetloadinghasbeenselected.

DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite

pointers are set to the first location of the FIFO. The FWFT pin selects IDT

PARTIAL RESET (PRS) MASTER RESET (MRS)

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

LOAD (LD)

DATA OUT (Q0 - Qn)

DATA IN (D0 - Dn)

IDT

72281

72291

RETRANSMIT (RT)

SERIAL ENABLE(SEN)

FIRST WORD FALL THROUGH/SERIAL INPUT

(FWFT/SI)

EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE ALMOST-EMPTY (PAE)

FULL FLAG/INPUT READY (FF/IR)

HALF-FULL FLAG (HF)

PROGRAMMABLE ALMOST-FULL (PAF)

4675 drw 03

Figure 1. Block Diagram of Single 65,536 x 9 and 131,072 x 9 Synchronous FIFO

1 234 5 6 7...26

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