Datasheet > 72271LA20TFG

72271LA20TFG

更新时间： 2024-02-08 19:14:25

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
27页	446K
描述
CMOS SuperSync FIFO

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中文翻译

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数据手册

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72271LA20TFG 数据手册

IDT72261LA/72271LA SuperSyncFIFO™

16,384 x 9 and 32,768 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0

to fMAX with complete independence. There are no restrictions on the

frequency of one clock input with respect to the other.

There are two possible timing modes of operation with these devices:

IDT Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard mode, the first word written to an empty FIFO will not

appear on the data output lines unless a specific read operation is

performed.Areadoperation,whichconsistsofactivatingRENandenabling

arisingRCLKedge,willshiftthewordfrominternalmemorytothedataoutput

lines.

DESCRIPTION (CONTINUED)

SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecom-

munications,datacommunicationsandotherapplicationsthatneedtobuffer

largeamountsofdata.

TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable

(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen

WENisasserted.TheoutputportiscontrolledbyaReadClock(RCLK)input

and Read Enable (REN) input. Data is read from the FIFO on every rising

edgeofRCLKwhenRENisasserted. AnOutputEnable(OE)inputisprovided

forthree-statecontroloftheoutputs.

PIN CONFIGURATIONS

PIN 1

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

DNC⁽³⁾

GND

DNC⁽³⁾

WEN

SEN

DC⁽¹⁾

VCC

GND⁽²⁾

VCC

DNC⁽³⁾

GND

DNC⁽³⁾

GND

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

4671 drw 02

TQFP (PN64-1, ORDER CODE: PF)

STQFP (PP64-1, ORDER CODE: TF)

TOP VIEW

NOTES:

1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.

2. This pin may either be tied to ground or left open.

3. DNC = Do Not Connect.

123 4 5 6 7...27

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