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72271

更新时间: 2023-12-20 18:44:33
品牌 Logo 应用领域
瑞萨 - RENESAS 先进先出芯片
页数 文件大小 规格书
28页 531K
描述
32K x 9 SuperSync FIFO, 5.0V

72271 数据手册

 浏览型号72271的Datasheet PDF文件第3页浏览型号72271的Datasheet PDF文件第4页浏览型号72271的Datasheet PDF文件第5页浏览型号72271的Datasheet PDF文件第7页浏览型号72271的Datasheet PDF文件第8页浏览型号72271的Datasheet PDF文件第9页 
IDT72261LA/72271LA SuperSyncFIFO™  
16,384 x 9 and 32,768 x 9  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
AC ELECTRICAL CHARACTERISTICS(1)  
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)  
Commercial  
Commercial & Industrial(2)  
IDT72261LA10  
IDT72271LA10  
IDT72261LA15  
IDT72271LA15  
Min.  
IDT72261LA20  
IDT72271LA20  
Symbol  
fS  
Parameter  
Clock Cycle Frequency  
Min.  
Max.  
100  
8
Max.  
66.7  
10  
15  
8
Min.  
Max.  
Unit  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2
2
2
50  
12  
20  
10  
10  
12  
12  
12  
12  
22  
tA  
DataAccessTime  
tCLK  
Clock Cycle Time  
10  
4.5  
4.5  
3
10  
6
15  
6
20  
8
tCLKH  
tCLKL  
tDS  
Clock High Time  
Clock Low Time  
6
8
DataSetupTime  
4
5
tDH  
DataHoldTime  
0
1
1
tENS  
tENH  
tLDS  
EnableSetupTime  
3
4
5
EnableHoldTime  
0
1
1
LoadSetupTime  
3
4
5
tLDH  
LoadHoldTime  
ResetPulseWidth(3)  
0
1
1
tRS  
10  
10  
10  
0
15  
15  
15  
0
20  
20  
20  
0
tRSS  
tRSR  
tRSF  
tFWFT  
tRTS  
tOLZ  
tOE  
ResetSetupTime  
ResetRecoveryTime  
ResettoFlagandOutputTime  
ModeSelectTime  
RetransmitSetupTime  
OutputEnabletoOutputinLowZ(4)  
OutputEnabletoOutputValid  
OutputEnabletoOutputinHighZ(4)  
Write Clock to FF or IR  
Read Clock to EF or OR  
Write Clock to PAF  
3
4
5
0
0
0
2
3
3
tOHZ  
tWFF  
tREF  
tPAF  
tPAE  
tHF  
2
6
3
8
3
5
8
6
10  
10  
10  
10  
20  
10  
20  
60  
25  
8
8
Read Clock to PAE  
8
Clock to HF  
16  
tSKEW1  
tSKEW2  
tSKEW3  
tSKEW4  
Skew time between RCLK and WCLK for FF/IR  
Skew time between RCLK and WCLK for PAE and PAF  
Skew time between RCLK and WCLK for EF/OR  
12  
60  
15  
15  
60  
17  
Skew time between RCLK and WCLK for PAE and PAF  
forRe-transmitoperation  
NOTES:  
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.  
2. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device.  
3. Pulse widths less than minimum values are not allowed.  
4. Values guaranteed by design, not currently tested.  
5V  
1.1K  
D.U.T.  
680Ω  
AC TEST CONDITIONS  
30pF*  
Input Pulse Levels  
GND to 3.0V  
3ns  
Input Rise/Fall Times  
Input Timing Reference Levels  
Output Reference Levels  
Output Load  
4671 drw 04  
1.5V  
1.5V  
Figure 2. Output Load  
See Figure 1  
* Includes jig and scope capacitances.  
6

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