IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTION
Symbol
D0–D8
MRS
Name
I/O
Description
DataInputs
I
I
Datainputsfora9-bitbus.
MasterReset
MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.
During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of
two programmable flag default settings, and serial or parallel programming of the offset settings.
PRS
RT
Partial Reset
Retransmit
I
I
PRS initializes the read and write pointers to zero and sets the output method (serial or parallel),
and programmable flag settings are all retained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming
method, existing timing mode or programmable flag settings. RT is useful to reread data from the
first physical location of the FIFO.
FWFT/SI
WCLK
First Word Fall
Write Clock
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. Through/Serial
In After Master Reset, this pin functions as a serial input for loading offset registers
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into
the programmable registers for parallel programming, and when enabled by SEN, the rising
edge of WCLK writes one bit of data into the programmable register for serial programming.
WEN
Write Enable
Read Clock
I
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets
fromtheprogrammableregisters.
REN
OE
Read Enable
OutputEnable
SerialEnable
Load
I
I
I
I
REN enablesRCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.
OEcontrolstheoutputimpedanceofQn.
SEN
LD
SENenablesserialloadingofprogrammableflagoffsets.
During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023) and determines
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to
andreadingfromtheoffsetregisters.
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master Reset.
FF/IR
Full Flag/
Input Ready
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory
is full. In the FWFT mode, the IR function isselected. IR indicates whether or not there is space
availableforwritingtotheFIFOmemory.
EF/OR
PAF
EmptyFlag/
OutputReady
O
O
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory
isempty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data
availableattheoutputs.
Programmable
Almost-FullFlag
PAF goes LOW if the number of words in the FIFO memory is more than word capacity of the FIFO
minusthefulloffsetvaluem,whichisstoredintheFullOffsetregister.Therearetwopossibledefault
values for m: 127 or 1,023.
PAE
Programmable
Almost-EmptyFlag
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the
Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values for n
canbeprogrammedintothedevice.
HF
Half-FullFlag
DataOutputs
Power
O
O
HF indicateswhethertheFIFOmemoryismoreorlessthanhalf-full.
Dataoutputsfora9-bus
Q0–Q8
VCC
+5 Volt power supply pins.
GND
Ground
Groundpins.
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