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72245LB15JG8 PDF预览

72245LB15JG8

更新时间: 2022-02-26 08:51:40
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
16页 338K
描述
CMOS SyncFIFO

72245LB15JG8 数据手册

 浏览型号72245LB15JG8的Datasheet PDF文件第2页浏览型号72245LB15JG8的Datasheet PDF文件第3页浏览型号72245LB15JG8的Datasheet PDF文件第4页浏览型号72245LB15JG8的Datasheet PDF文件第6页浏览型号72245LB15JG8的Datasheet PDF文件第7页浏览型号72245LB15JG8的Datasheet PDF文件第8页 
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM  
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
ACELECTRICALCHARACTERISTICS  
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)  
Commercial  
Commercial & Industrial(1)  
IDT72205LB10  
IDT72215LB10  
IDT72225LB10  
IDT72235LB10  
IDT72245LB10  
IDT72205LB15  
IDT72205LB25  
IDT72215LB25  
IDT72225LB25  
IDT72235LB25  
IDT72245LB25  
IDT72215LB15  
IDT72225LB15  
IDT72235LB15  
IDT72245LB15  
Symbol  
fS  
Parameter  
Clock Cycle Frequency  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2
100  
6.5  
15  
6
2
66.7  
10  
20  
8
2
40  
15  
25  
12  
12  
15  
15  
26  
26  
26  
15  
tA  
DataAccessTime  
tCLK  
tCLKH  
tCLKL  
tDS  
Clock Cycle Time  
10  
4.5  
4.5  
3
15  
6
25  
10  
10  
6
Clock HIGH Time  
Clock LOW Time  
6
DataSet-upTime  
4
tDH  
DataHoldTime  
0
1
1
tENS  
tENH  
tRS  
EnableSet-upTime  
3
4
6
EnableHoldTime  
ResetPulseWidth(2)  
0
1
1
10  
8
15  
10  
10  
0
25  
15  
15  
0
tRSS  
tRSR  
tRSF  
tOLZ  
tOE  
ResetSet-upTime  
ResetRecoveryTime  
8
ResettoFlagandOutputTime  
OutputEnabletoOutputinLow-Z(3)  
OutputEnabletoOutputValid  
OutputEnabletoOutputinHigh-Z(3)  
Write Clock to Full Flag  
0
3
3
3
tOHZ  
tWFF  
tREF  
tPAF  
tPAE  
tHF  
3
6
3
8
3
3
6.5  
6.5  
17  
17  
17  
6.5  
6.5  
5
10  
10  
24  
24  
24  
10  
10  
10  
10  
10  
Read Clock to Empty Flag  
ClocktoAsynchronousProgrammableAlmost-FullFlag  
Clock to Programmable Almost-Empty Flag  
Clock to Half-Full Flag  
tXO  
Clock to Expansion Out  
tXI  
Expansion In Pulse Width  
Expansion In Set-Up Time  
Skew time between Read Clock & Write Clock forFull Flag  
Skew time between Read Clock & Write Clock for Empty Flag  
tXIS  
3.5  
5
tSKEW1  
6
(2)  
tSKEW2  
5
6
NOTES:  
1. Industrial temperature range product for the 15ns and the 25ns speed grades are available as a standard device. All other speed grades are available by special order.  
2. Pulse widths less than minimum values are not allowed.  
3. Values guaranteed by design, not currently tested.  
5V  
1.1K  
D.U.T.  
30pF*  
680Ω  
ACTESTCONDITIONS  
InputPulseLevels  
GND to 3.0V  
3ns  
1.5V  
1.5V  
SeeFigure1  
2766 drw 04  
InputRise/FallTimes  
InputTimingReferenceLevels  
OutputReferenceLevels  
OutputLoad  
Figure 1. Output Load  
Includes jig and scope capacitances.  
*
5
MARCH 2013  

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