256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
ZBT™Feature
IDT71V65603
IDT71V65803
3.3V I/O, Burst Counter
PipelinedOutputs
Features
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.
TheIDT71V65603/5803containdataI/O,addressandcontrolsignal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
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256K x 36, 512K x 18 memory configurations
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Supports high performance system speed - 150MHz
(3.8ns Clock-to-Data Access)
ZBT Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V I/O Supply (VDDQ)
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array(fBGA).
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TM
AClockEnable(CEN)pinallowsoperationoftheIDT71V65603/5803to
besuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen
(CEN)ishighandtheinternaldeviceregisterswillholdtheirpreviousvalues.
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
todeselectthedevicewhendesired.Ifanyoneofthesethreearenotasserted
whenADV/LDislow,nonewmemoryoperationcanbeinitiated.However,
anypendingdatatransfers(readsorwrites)willbecompleted.Thedatabus
willtri-statetwocyclesafterchipisdeselectedorawriteisinitiated.
TheIDT71V65603/5803haveanon-chipburstcounter.Intheburst
mode,theIDT71V65603/5803canprovidefourcyclesofdataforasingle
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LDsignal is used to load a new
externaladdress(ADV/LD=LOW) orincrementtheinternalburstcounter
(ADV/LD = HIGH).
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Description
The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit
(9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbus
cycleswhenturningthebusaroundbetweenreadsandwrites,orwritesand
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-
pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA)and
165 fine pitch ball grid array (fBGA).
TM
reads.Thus,theyhavebeengiventhenameZBT ,orZeroBusTurnaround.
PinDescriptionSummary
A0-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE , CE2, CE
1
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW1, BW2, BW3, BW4
CLK
ADV/LD
Advance burst address / Load new address
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Static
LBO
ZZ
Asynchronous
Synchronous
Static
I/O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
Data Input / Output
Core Power, I/O Power
Ground
Supply
Supply
V
SS
Static
5304 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
SEPTEMBER 2004
MARCH 2009
1
©2004IntegratedDeviceTechnology,Inc.
DSC-5304/06
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