Datasheet > 71V416VL12BEGI

71V416VL12BEGI

更新时间： 2023-04-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
9页	980K
描述
Standard SRAM, 256KX16, 12ns, CMOS, PBGA48, 9 X 9 MM, ROHS COMPLIANT, BGA-48

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71V416VL12BEGI 数据手册

3.3V CMOS Static RAM

4 Meg (256K x 16-Bit)

IDT71V416VS

IDT71V416VL

Description

Features

◆

TheIDT71V416isa4,194,304-bithigh-speedStaticRAMorganized

as256Kx16.ItisfabricatedusingIDT’shigh-perfomance,high-reliability

CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-

vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-

speedmemoryneeds.

256K x 16 advanced high-speed CMOS Static RAM

◆

JEDEC Center Power / GND pinout for reduced noise.

Equal access and cycle times

◆

– CommercialandIndustrial:10/12/15ns

One Chip Select plus one Output Enable pin

Bidirectional data inputs and outputs directly

◆

TheIDT71V416has anoutputenablepinwhichoperates as fastas

5ns,withaddressaccesstimesasfastas10ns.Allbidirectionalinputsand

outputsoftheIDT71V416areLVTTL-compatibleandoperationisfroma

single3.3Vsupply.Fullystaticasynchronouscircuitryisused,requiring

noclocks orrefreshforoperation.

The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a

44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x

9mmpackage.

LVTTL-compatible

Low power consumption via chip deselect

Upper and Lower Byte Enable Pins

Single 3.3V power supply

◆

Available in 44-pin, 400 mil plastic SOJ package and a 44-

pin, 400 mil TSOP Type II package and a 48 ball grid array,

9mm x 9mm package.

FunctionalBlockDiagram

Output

Enable

Buffer

Address

Buffers

Row / Column

Decoders

A0 - A17

High

Byte

I/O 15

I/O 8

Output

Chip

Select

Buffer

High

Byte

Write

Sense

Amps

and

Write

Drivers

4,194,304-bit

Memory

Array

Buffer

Write

Enable

Buffer

Low

Byte

I/O 7

I/O 0

Output

Buffer

Low

Byte

Write

Buffer

BHE

BLE

Byte

Enable

Buffers

6478 drw 01

OCTOBER 2008

DSC-6478/00

12 3 4 5 6 7...9

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