Datasheet > 71V416S12BEG8

71V416S12BEG8

更新时间： 2022-12-29 19:55:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
9页	645K
描述
3.3V CMOS Static RAM

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71V416S12BEG8 数据手册

IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM

4 Meg (256K x 16-Bit)

Commercial and Industrial Temperature Ranges

DC Electrical Characteristics

(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)

IDT71V416

Symbol

Parameter

Input Leakage Current

Test Conditions

Min.

___

Max.

Unit

µA

|ILI

CC = Max., VIN =

SS to VDD

___

|I^LO

Output Leakage Current

Output Low Voltage

Output High Voltage

DD = Max., CS = VIH, VOUT = VSS to VDD

VOL

OL = 8mA, VDD = Min.

OH = -4mA, VDD = Min.

0.4

___

VOH

2.4

3624 tbl 07

DC Electrical Characteristics^{(1, 2, 3)}

(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)

71V416S/L10

Com'l. Ind.

200 200

71V416S/L12

Com'l. Ind.

180 180

71V416S/L15

Com'l.

170

160

Ind.

170

160

Symbol

Parameter

Unit

ICC

Dynamic Operating Current

(4)

CS < VLC, Outputs Open, VDD = Max., f = fMAX

180

170

ISB

Dynamic Standby Power Supply Current

CS > VHC, Outputs Open, VDD = Max., f = fMAX

ISB1

Full Standby Power Supply Current (static)

CS > VHC, Outputs Open, VDD = Max., f = 0⁽⁴⁾

3624 tbl 08

NOTES:

IDT71V416S/71V416L

1. All values are maximum guaranteed values.

2. All inputs switch between 0.2V (Low) and VDD -0.2V (High).

3. Power specifications are preliminary.

4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.

AC Test Loads

3.3V

320

+1.5V

Ω

50Ω

OUT

DATA

I/O

Z0 = 50Ω

5pF*

350Ω

30pF

3624 drw 03

3624 drw 04

Figure 1. AC Test Load

*Including jig and scope capacitance.

Figure 2. AC Test Load

(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)

•

AC Test Conditions

∆t^AA,

tACS

(Typical, ns)

Input Pulse Levels

GND to 3.0V

1.5ns

•

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

AC Test Load

•

1.5V

•

1.5V

180

8 20 40 60 80 100 120 140 160

CAPACITANCE (pF)

200

3624 drw 05

Figures 1,2 and 3

3624 tbl 09

Figure 3. Output Capacitive Derating

6.42

1 2 345 6 7...9

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