Datasheet > 71V2558XS100BQG

71V2558XS100BQG

更新时间： 2023-07-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
28页	567K
描述
ZBT SRAM, 256KX18, 5ns, CMOS, PBGA165, 15 X 13 MM, ROHS COMPLIANT, FBGA-165

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71V2558XS100BQG 数据手册

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

with 2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

JTAG Interface Specification (SA Version only)

JCYC

tJF

tJCL

tJCH

TCK

Device Inputs⁽¹⁾/

TDI/TMS

tJDC

tJS

tJH

Device Outputs⁽²⁾/

TDO

JRSR

tJCD

(

TRST

M4875 drw 01

JRST

NOTES:

1. Device inputs = All device inputs except TDI, TMS and TRST.

2. Device outputs = All device outputs except TDO.

3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

JTAG AC Electrical

Characteristics^(1,2,3,4)

Symbol

Parameter

JTAG Clock Input Period

JTAG Clock HIGH

JTAG Clock Low

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset

Min.

100

Max.

Units

ScanRegisterSizes

____

JCYC

JCH

JCL

JRST

JRSR

JCD

JDC

Bit Size

____

Instruction (IR)

Bypass (BYR)

(1)

____

JTAG Identification (JIDR)

Boundary Scan (BSR)

(1)

____

Note (1)

____

I4875 tbl 03

JTAG Reset Recovery

JTAG Data Output

JTAG Data Output Hold

JTAG Setup

NOTE:

1. The Boundary Scan Descriptive Language (BSDL) file for this device is available

by contacting your local IDT sales representative.

____

JTAG Hold

I4875 tbl 01

NOTES:

1. Guaranteed by design.

2. AC Test Load (Fig. 1) on external output signals.

3. Refer to AC Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

6.2422

1...19 20 212223 24 25...28

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