5秒后页面跳转
捷配首页

Datasheet > 71V2546XS150PFG8
71V2546XS150PFG8 PDF预览

71V2546XS150PFG8

更新时间： 2024-11-17 00:32:55
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
21页 733K
描述
3.3V Synchronous ZBT SRAM

阅读下载

中文翻译

获取价格

71V2546XS150PFG8 数据手册

 浏览型号71V2546XS150PFG8的Datasheet PDF文件第2页浏览型号71V2546XS150PFG8的Datasheet PDF文件第3页浏览型号71V2546XS150PFG8的Datasheet PDF文件第4页浏览型号71V2546XS150PFG8的Datasheet PDF文件第5页浏览型号71V2546XS150PFG8的Datasheet PDF文件第6页浏览型号71V2546XS150PFG8的Datasheet PDF文件第7页 
IDT71V2546S/XS  
128K x 36  
3.3V Synchronous ZBT™ SRAM  
2.5V I/O, Burst Counter  
Pipelined Outputs  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle, andtwocycleslatertheassociateddatacycleoccurs, beitread  
or write.  
Features  
◆
128K x 36 memory configurations  
◆
Supports high performance system speed - 150 MHz  
The IDT71V2546 contains data I/O, address and control signal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
(3.8 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
◆
cycles  
◆
AClockEnable(CEN)pinallowsoperationoftheIDT71V2546tobe  
suspended as long as necessary. All synchronous inputs are ignored  
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
Internally synchronized output buffer enable eliminates the  
need to control OE  
◆
Single R/W (READ/WRITE) control pin  
◆
Positive clock-edge triggered address, data, and control  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
to deselect the device when desired. If any one of these three are not  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-statetwocyclesafterchipisdeselectedorawriteis  
initiated.  
signal registers for fully pipelined applications  
◆
4-word burst capability (interleaved or linear)  
◆
Individual byte write (BW1 - BW4) control (May tie active)  
◆
Three chip enables for simple depth expansion  
◆
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)  
◆
Packaged in a JEDEC standard 100-pin plastic thin quad  
TheIDT71V2546hasanon-chipburstcounter.Intheburstmode,the  
IDT71V2546 can provide four cycles of data for a single address  
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe  
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst  
sequence. The ADV/LD signal is used to load a new external address  
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =  
HIGH).  
flatpack (TQFP) and 119 ball grid array (BGA)  
Description  
The IDT71V2546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)  
synchronous SRAM. It is designed to eliminate dead bus cycles when  
turning the bus around between reads and writes, or writes and reads.  
Thus, theyhavebeengiventhenameZBTTM, orZeroBusTurnaround.  
TheIDT71V2546SRAMutilizeIDT's latesthigh-performanceCMOS  
process and is packaged in a JEDEC standard 14mm x 20mm 100-pin  
thinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA).  
PinDescriptionSummary  
A0-A16  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE , CE  
1
2
, CE  
2
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
ZZ  
Synchronous  
Synchronous  
Static  
I/O  
0
-I/O31, I/OP1-I/OP4  
DD, VDDQ  
SS  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
Supply  
Supply  
V
Static  
5294 tbl 01  
APRIL 2011  
1
©2011IntegratedDeviceTechnology,Inc.  
DSC-5294/07  
1234567...21

中文翻译

下载PDF

与71V2546XS150PFG8相关器件

型号 品牌 获取价格 描述 数据表
71V2546XS150PFGI IDT

获取价格

 		3.3V Synchronous ZBT SRAM
71V2546XS150PFGI8 IDT

获取价格

 		3.3V Synchronous ZBT SRAM
71V2546XSA100BQ IDT

获取价格

 		ZBT SRAM, 128KX36, 5ns, CMOS, PBGA165
71V2546XSA100BQI IDT

获取价格

 		ZBT SRAM, 128KX36, 5ns, CMOS, PBGA165
71V2546XSA133BG IDT

获取价格

 		ZBT SRAM, 128KX36, 4.2ns, CMOS, PBGA119
71V2546XSA133BGI IDT

获取价格

 		ZBT SRAM, 128KX36, 4.2ns, CMOS, PBGA119
71V2546XSA133BQ IDT

获取价格

 		ZBT SRAM, 128KX36, 4.2ns, CMOS, PBGA165
71V2546XSA150BG IDT

获取价格

 		ZBT SRAM, 128KX36, 3.8ns, CMOS, PBGA119
71V2546XSA150BQ IDT

获取价格

 		ZBT SRAM, 128KX36, 3.8ns, CMOS, PBGA165
71V2548S100BG IDT

获取价格

 		PBGA-119, Tray

与71V2546XS150PFG8相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证