71T75802S150BGGI PDF预览

71T75802S150BGGI

更新时间: 2025-09-21 19:36:11
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟存储
页数 文件大小 规格书
28页 314K
描述
存储容量(Mb):18Mb(1M x 18);内存数据长度(bit):1M ;字编码数(k):1M ;最大时钟频率(MHz):150 MHz;元器件封装:119-PBGA(14x22);

71T75802S150BGGI 数据手册

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512K x 36, 1M x 18  
71T75602  
71T75802  
2.5VSynchronousZBTSRAMs  
2.5V I/O, Burst Counter  
PipelinedOutputs  
Features  
512K x 36, 1M x 18 memory configurations  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
2.5V power supply (±5%)  
2.5V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA)  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Supports high performance system speed - 200 MHz  
(3.2 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Green parts available, see ordering information  
Functional Block Diagram - 512K x 36  
LBO  
512Kx36 BIT  
MEMORY ARRAY  
Address A [0:18]  
D
D
Q
Q
Address  
CE1, CE2, CE2  
R/W  
Control  
CEN  
ADV/LD  
BW  
DI DO  
x
D
Q
Control Logic  
Clk  
Mux  
Sel  
D
Clock  
Output Register  
Q
Gate  
OE  
TMS  
TDI  
Data I/O [0:31],  
I/O P[1:4]  
JTAG  
TDO  
TCK  
TRST  
5313 drw 01  
(optional)  
ZBT® andZeroBusTurnaroundaretrademarksofRenesasElectronicsCorporationandthearchitectureissupportedbyMicronTechnologyandMotorolaInc.  
1
Sep.27.21  

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