Datasheet > 71T016SA10PHGI8

71T016SA10PHGI8

更新时间： 2024-02-02 23:40:48

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
9页	99K
描述
TSOP-44, Reel

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技术参数
数据手册

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71T016SA10PHGI8 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	TSOP
包装说明：	,	针数：	44
Reach Compliance Code：	compliant	风险等级：	5.83
JESD-609代码：	e3	内存集成电路类型：	STANDARD SRAM
湿度敏感等级：	3	峰值回流温度（摄氏度）：	260
端子面层：	Matte Tin (Sn)	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

71T016SA10PHGI8 数据手册

IDT71T016SA, 2.5V CMOS Static RAM

1 Meg (64K x 16-Bit)

Commercial and Industrial Temperature Ranges

Timing Waveform of Read Cycle No. 2⁽¹⁾

tRC

ADDRESS

tAA

tOH

(3)

tOHZ

tOE

(3)

tOLZ

(2)

tACS

(3)

tCHZ

tCLZ

BLE

BHE,

(2)

(3)

tBE

tBHZ

(3)

tBLZ

DATAOUT

DATA OUTVALID

5326 drw 07

NOTES:

1. WE is HIGH for Read Cycle.

2. AddressmustbevalidpriortoorcoincidentwiththelaterofCS,BHE,orBLE transitionLOW;otherwisetAA isthelimitingparameter.

3. Transitionismeasured±200mVfromsteadystate.

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)^(1,2,4)

tWC

ADDRESS

tAW

(2)

(5)

tCW

tCHZ

tBHZ

tBW

BHE _,BLE

tWR

tWP

tAS

(5)

tWHZ

(5)

tOW

tDH

(3)

DATAOUT

PREVIOUS DATA VALID

DATA VALID

tDW

DATAIN

DATAIN VALID

5326 drw 08

NOTES:

1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.

2. OEis continuouslyHIGH. IfduringaWE controlledwrite cycleOEis LOW, tWP mustbe greaterthanorequaltotWHZ+tDW toallowthe I/Odrivers toturnoffanddata tobe placed

onthe bus forthe requiredtDW. IfOEis HIGHduringaWEcontrolledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is as shortas the specifiedtWP.

3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.

4. IftheCSLOWorBHEandBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.

5. Transitionismeasured±200mVfromsteadystate.

6.42

1...3 4 567 8 9

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