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71P73604S300BQ PDF预览

71P73604S300BQ

更新时间： 2024-10-02 19:42:19
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
24页 362K
描述
CABGA-165, Tray

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71P73604S300BQ 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：CABGA
包装说明：BGA, BGA165,11X15,40针数：165
Reach Compliance Code：not_compliant风险等级：5.92
最长访问时间：0.45 ns最大时钟频率 (fCLK)：300 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e0内存密度：18874368 bit
内存集成电路类型：STANDARD SRAM内存宽度：36
湿度敏感等级：3端子数量：165
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS组织：512KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：225
电源：1.5/1.8,1.8 V认证状态：Not Qualified
最小待机电流：1.7 V子类别：SRAMs
表面贴装：YES技术：CMOS
端子面层：TIN LEAD端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20Base Number Matches：1

71P73604S300BQ 数据手册

 浏览型号71P73604S300BQ的Datasheet PDF文件第2页浏览型号71P73604S300BQ的Datasheet PDF文件第3页浏览型号71P73604S300BQ的Datasheet PDF文件第4页浏览型号71P73604S300BQ的Datasheet PDF文件第5页浏览型号71P73604S300BQ的Datasheet PDF文件第6页浏览型号71P73604S300BQ的Datasheet PDF文件第7页 
Advance  
Information  
IDT71P73204  
IDT71P73104  
IDT71P73804  
IDT71P73604  
18Mb Pipelined  
DDR™II SRAM  
Burst of 4  
Features  
Description  
TM  
◆
◆
◆
◆
◆
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)  
Common Read and Write Data Port  
Dual Echo Clock Output  
4-Word Burst on all SRAM accesses  
Multiplexed Address Bus  
The IDT DDRII Burst of four SRAMs are high-speed synchronous  
memories with a double-data-rate (DDR), bidirectional data port. This  
scheme allows maximization on the bandwidth on the data bus by pass-  
ing two data items per clock cycle. The address bus operates at single  
data rate speeds,allowing the user to fan out addresses and ease system  
design while maintaining maximum performance on data transfers.  
The DDRII has scalable output impedance on its data output bus and  
echo clocks, allowing the user to tune the bus for low noise and high  
performance.  
-
One Read or One Write request per two clock  
cycles.  
DDR (Double Data Rate) Data Bus  
Four word bursts data per two clock cycles  
◆
-
◆
◆
Depth expansion through Control Logic  
HSTL (1.5V) inputs that can be scaled to receive signals  
from 1.4V to 1.9V.  
All interfaces of the DDRII SRAM are HSTL, allowing speeds be-  
yond SRAM devices that use any form of TTL interface. The interface  
can be scaled to higher voltages (up to 1.9V) to interface with 1.8 sys-  
tems if necessary. The device has a VDDQanda separate Vref, allowing  
the user to designate the interface operational voltage, independent of  
the device core voltage of 1.8V VDD. The output impedance control  
allows the user to adjust the drive strength to adapt to a wide range of  
loads and transmission lines.  
◆
Scalable output drivers  
-
Can drive HSTL, 1.8V TTL or any voltage level  
from 1.4V to 1.9V.  
-
Output Impedance adjustable from 35 ohms to 70  
ohms  
◆
◆
◆
1.8V Core Voltage (VDD)  
JTAG Interface  
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package  
Clocking  
The DDRII SRAM has two sets of input clocks, namely the K, K clocks  
and the C, C clocks. In addition, the QDRII has an output “echo” clock,  
CQ, CQ.  
The K and K clocks are the primary device input clocks. The K  
clock is used to clock in the control signals (LD, R/W andBWx or  
NWx), the address, and the first and third words of the data burst  
during a write operation. The K clock is used to clock in the control  
Functional Block Diagram  
DATA  
REG  
(Note1)  
WRITE DRIVER  
(Note2)  
SA  
SA  
ADD  
REG  
(Note2)  
0
1
SA  
(Note4)  
(Note4)  
(Note1)  
18M  
MEMORY  
ARRAY  
DQ  
LD  
RW  
BWx  
CTRL  
LOGIC  
(Note3)  
K
CLK  
GEN  
CQ  
K
CQ  
C
SELECT OUTPUT CONTROL  
C
6431 drw 16  
Notes  
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36  
2) Represents 19 address signal lines for x8 and x9, 18 address signal lines for x18, and 17 address signal lines for x36.  
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2  
signal lines.  
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.  
MAY 2004  
1
©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “  
DSC-6431/00  
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