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71P73604S250BQ8 PDF预览

71P73604S250BQ8

更新时间: 2024-10-02 20:07:59
品牌 Logo 应用领域
艾迪悌 - IDT 时钟双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
25页 637K
描述
CABGA-165, Reel

71P73604S250BQ8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:CABGA
包装说明:13 X 15 MM, 1 MM PITCH, FBGA-165针数:165
Reach Compliance Code:not_compliant风险等级:5.92
最长访问时间:0.45 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):250 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B165JESD-609代码:e0
长度:15 mm内存密度:18874368 bit
内存集成电路类型:DDR SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:165字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TBGA
封装等效代码:BGA165,11X15,40封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:1.5/1.8,1.8 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.325 A最小待机电流:1.7 V
子类别:SRAMs最大压摆率:0.8 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:13 mm
Base Number Matches:1

71P73604S250BQ8 数据手册

 浏览型号71P73604S250BQ8的Datasheet PDF文件第2页浏览型号71P73604S250BQ8的Datasheet PDF文件第3页浏览型号71P73604S250BQ8的Datasheet PDF文件第4页浏览型号71P73604S250BQ8的Datasheet PDF文件第5页浏览型号71P73604S250BQ8的Datasheet PDF文件第6页浏览型号71P73604S250BQ8的Datasheet PDF文件第7页 
IDT71P73204  
IDT71P73104  
IDT71P73804  
IDT71P73604  
18Mb Pipelined  
DDR™II SRAM  
Burst of 4  
Features  
Description  
The IDT DDRIITM Burst of four SRAMs are high-speed synchro-  
nous memories with a double-data-rate (DDR), bidirectional data port.  
This scheme allows maximization on the bandwidth on the data bus by  
passing two data items per clock cycle. The address bus operates at  
less than single data rate speeds,allowing the user to fan out addresses  
and ease system design while maintaining maximum performance on  
data transfers.  
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)  
Common Read and Write Data Port  
Dual Echo Clock Output  
4-Word Burst on all SRAM accesses  
MultiplexedAddress Bus  
-
One Read or One Write request per two clock  
cycles.  
DDR (Double Data Rate) Data Bus  
Four word bursts data per two clock cycles  
The DDRII has scalable output impedance on its data output bus  
and echo clocks, allowing the user to tune the bus for low noise and high  
performance.  
-
Depth expansion through Control Logic  
HSTL (1.5V) inputs that can be scaled to receive signals  
from 1.4V to 1.9V.  
All interfaces of the DDRII SRAM are HSTL, allowing speeds  
beyond SRAM devices that use any form of TTL interface. The inter-  
face can be scaled to higher voltages (up to 1.9V) to interface with 1.8V  
systems if necessary. The device has a VDDQ and a separate Vref,  
allowing the user to designate the interface operational voltage, inde-  
pendent of the device core voltage of 1.8V VDD. Theoutput impedance  
control allows the user to adjust the drive strength to adapt to a wide  
range of loads and transmission lines.  
Scalable output drivers  
-
Can drive HSTL, 1.8V TTL or any voltage level  
from 1.4V to 1.9V.  
Output Impedance adjustable from 35 ohms to 70  
ohms  
-
1.8V Core Voltage (VDD)  
JTAG Interface  
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package  
Functional Block Diagram  
DATA  
REG  
(Note1)  
WRITE DRIVER  
(Note2)  
SA  
ADD  
REG  
(Note2)  
SA0  
SA  
1
(Note4)  
(Note4)  
(Note1)  
18M  
MEMORY  
ARRAY  
DQ  
LD  
RW  
BWx  
CTRL  
LOGIC  
(Note3)  
K
K
CLK  
GEN  
CQ  
CQ  
C
SELECT OUTPUT CONTROL  
C
6431 drw 16  
Notes  
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36  
2) Represents 19 address signal lines for x8 and x9, 20 address signal lines for x18, and 19 address signal lines for x36.  
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write and there are 2  
signal lines.  
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.  
JULY 2005  
1
©2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.“  
DSC-6431/00  

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