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7143LA25JB PDF预览

7143LA25JB

更新时间: 2024-02-02 13:41:21
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
16页 137K
描述
Dual-Port SRAM, 2KX16, 25ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68

7143LA25JB 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:LCC
包装说明:QCCJ, LDCC68,1.0SQ针数:68
Reach Compliance Code:not_compliantECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.21
Is Samacsys:N最长访问时间:25 ns
I/O 类型:COMMONJESD-30 代码:S-PQCC-J68
JESD-609代码:e0长度:24.2062 mm
内存密度:32768 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16湿度敏感等级:1
功能数量:1端口数量:2
端子数量:68字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:2KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC68,1.0SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified筛选级别:MIL-PRF-38535
座面最大高度:4.572 mm最大待机电流:0.004 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.3 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:24.2062 mmBase Number Matches:1

7143LA25JB 数据手册

 浏览型号7143LA25JB的Datasheet PDF文件第5页浏览型号7143LA25JB的Datasheet PDF文件第6页浏览型号7143LA25JB的Datasheet PDF文件第7页浏览型号7143LA25JB的Datasheet PDF文件第9页浏览型号7143LA25JB的Datasheet PDF文件第10页浏览型号7143LA25JB的Datasheet PDF文件第11页 
IDT7133SA/LA,IDT7143SA/LA  
High-Speed 2K x 16 Dual-Port RAM  
Military, Industrial and Commercial Temperature Ranges  
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(5)  
tRC  
ADDRESS  
t
AA  
tOH  
tOH  
DATAOUT  
PREVIOUS DATA VALID  
DATA VALID  
BUSYOUT  
(3,4)  
2746 drw 07  
tBDD  
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(5)  
(4)  
tACE  
CE  
OE  
(4)  
(2)  
tAOE  
tHZ  
(1)  
(2)  
tLZ  
tHZ  
DATAOUT  
VALID DATA  
(1)  
tLZ  
tPU  
tPD  
ICC  
CURRENT  
50%  
50%  
ISB  
2746 drw 08  
NOTES:  
1. Timing depends on which signal is asserted last, OE or CE.  
2. Timing depends on which signal is deasserted first, OE or CE.  
3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no  
relationship to valid output data.  
4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD.  
5. R/W = VIH, and the address is valid prior to or coincidental with CE transition LOW.  
6.42  
8

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