Datasheet > 71342LA20PF8

71342LA20PF8

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
14页	124K
描述
TQFP-64, Reel

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71342LA20PF8 数据手册

IDT71342SA/LA

High-Speed 4K x 8 Dual-Port Static RAM with Semaphore

Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle No. 1, Either Side^(1,2,4)

tRC

ADDRESS

AA or tSAA

tOH

DATAOUT

PREVIOUS DATA VALID

DATA VALID

2721 drw 07

Timing Waveform of Read Cycle No. 2, Either Side^(1,3)

SOP

tACE

CE or SEM ⁽⁵⁾

(2)

(4)

AOE

tSOP

tHZ

(2)

(1)

tHZ

tLZ

DATAOUT

VALID DATA⁽⁴⁾

(1)

tPU

tPD

CURRENT

50%

2721 drw 08

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, OE or CE.

3. R/W = V^IHand OE = VIL, unless otherwise noted.

4. Start of valid data depends on which timing becomes effective last; t^AOE, tACE, or tAA

5. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tAA is for SRAM Address Access and tSAA is for Semaphore Address Access.

Timing Waveform of Write with Port-to-Port Read^(2,3)

ADDR "A"

MATCH

(1)

R/W "A"

tDH

DATAIN "A"

ADDR "B"

VALID

MATCH

WDD

VALID

DATAOUT "B"

DDD

2721 drw 09

NOTES:

1. Write cycle parameters should be adhered to, in order to ensure proper writing.

2. CE^{L =}CER = VIL. CE"B" = VIL.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6.42

1...4 5 678 9 10...14

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