Datasheet > 70V9159L9PFGI

70V9159L9PFGI

更新时间： 2022-12-29 20:46:23

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	205K
描述
HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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70V9159L9PFGI 数据手册

IDT70V9169/59L

High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle for Flow-Through Output

(FT/PIPE"X" = VIL)^(3,6)

tCYC1

tCH1

tCL1

CLK

tSC

tHC

tSC

tHC

CE1

R/W

tHW

tSW

tSA

tHA

ADDRESS⁽⁵⁾

DATAOUT

An + 1

An + 2

An + 3

(1)

tDC

tCD1

tCKHZ

Qn + 1

Qn + 2

(1)

tCKLZ

tDC

(1)

tOHZ

tOLZ

OE⁽²⁾

tOE

5655 drw 07

Timing Waveform of Read Cycle for Pipelined Operation

(FT/PIPE"X" = VIH)^(3,6)

tCYC2

tCH2

tCL2

CLK

tSC

tHC

tSC

(4)

CE1

R/W

tHW

tSW

tSA

tHA

ADDRESS⁽⁵⁾

An + 1

An + 2

An + 3

(1 Latency)

tDC

tCD2

Qn + 2 ⁽⁶⁾

DATAOUT

Qn + 1

(1)

tCKLZ

(1)

OHZ

tOLZ

OE⁽²⁾

tOE

5655 drw 08

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

3. ADS = VIL, CNTEN and CNTRST = VIH.

4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL following the next rising edge of the clock. Refer to Truth Table 1.

5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

6. "X' here denotes Left or Right port. The diagram is with respect to that port.

6.42

1...6 7 8910 11 12...16

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