Datasheet > 70V9159L9PFGI

70V9159L9PFGI

更新时间： 2022-12-29 20:46:23

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	205K
描述
HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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70V9159L9PFGI 数据手册

IDT70V9169/59L

High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range ( VDD= 3.3V ± 0.3V)

70V9169/59L

Symbol

|I^LI

|I^LO

Parameter

Input Leakage Current⁽¹⁾

Output Leakage Current

Output Low Voltage

Test Conditions

Min.

Max.

Unit

µA

___

DD = 3.6V, VIN = 0V t

CE = V^IHor CE = VIL, VOUT = 0V t

OL = +4mA

OH = -4mA

o VDD

0.4

___

Output High Voltage

2.4

5655 tbl 08

NOTE:

1. At V^DD< 2.0V input leakages are undefined.

DC Electrical Characteristics Over the Operating

Temperature Supply Voltage Range⁽³⁾(VDD = 3.3V ± 0.3V)

70V9169/59L6

Com'l Only

70V9169/59L7

Com'l & Ind

70V9169/59L9

Com'l Only

Symbol

Parameter

Test Condition

and CE = VIL

Version

COM'L

Typ.⁽⁴⁾

Max.

Typ.⁽⁴⁾

Max.

280

330

Typ.⁽⁴⁾

Max.

Unit

IDD

Dynamic Operating

Current (Both

Ports Active)

175

330

155

135

230

Outputs Disabled,

f = fMAX

(1)

____

IND

ISB1

Standby Current

(Both Ports - TTL

Level Inputs)

COM'L

IND

L = CER = VIH

(1)

____

f = fMAX

ISB2

Standby

CE"A" = VIL and

COM'L

IND

115

185

105

170

155

(5)

Current (One

Port - TTL

Level Inputs)

CE"B" = VIH

Active Port Outputs

Disabled, f=fMAX

____

105

0.5

180

3.0

160

(1)

ISB3

Full Standby

Current (Both

Ports - CMOS

Level Inputs)

Both Ports CEL

CE >VDD - 0.2V,

and

COM'L

IND

0.5

3.0

0.5

3.0

IN > VDD- 0.2V or

IN < 0.2V, f = 0⁽²⁾

____

ISB4

Full Standby

Current (One

Port - CMOS

Level Inputs)

COM'L

IND

105

175

145

CE"A" < 0.2V and

CE"B" > VDD - 0.2V⁽⁵⁾

IN > VDD- 0.2V or

IN < 0.2V, Active Port,

____

175

Outputs Disabled, f = fMAX

(1)

5655 tbl 09

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. V^DD=3.3V,TA =25°C forTyp,andarenotproductiontested.ICC DC(f=0)=90mA(Typ).

5. CEX = VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CE^X< 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V

CE^X> VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V

"X" represents "L" for left port or "R" for right port.

6.462

1...3 4 567 8 9...16

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