Datasheet > 70V9159L9BFGI8

70V9159L9BFGI8

更新时间： 2022-12-29 20:46:23

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	205K
描述
HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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70V9159L9BFGI8 数据手册

IDT70V9169/59L

High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)⁽³⁾

CYC1

tCH1

tCL1

CLK

CE0

tSC

tHC

CE1

tSW tHW

R/W

(4)

An + 4

An + 3

An +1

An + 2

ADDRESS

tSD

tHD

DATAIN

Dn + 2

CD1

tCD1

(2)

Qn + 3

Qn + 1

DATAOUT

(1)

CKLZ

(1)

tDC

CKHZ

NOP⁽⁵⁾

READ

WRITE

5655 drw 13

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)⁽³⁾

tCYC1

tCH1

tCL1

CLK

tSC

tHC

SW tHW

R/W

tSW tHW

(4)

An + 2

An + 4

An + 5

An + 3

Dn + 3

tHA

An +1

ADDRESS

tSA

SD tHD

DATAIN

Dn + 2

tOE

tDC

tCD1

(2)

Qn + 4

DATAOUT

(1)

CKLZ

(1)

tOHZ

tDC

READ

WRITE

READ

5655 drw 14

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".

4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

6.1422

1...9 10 111213 14 15 16

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