Datasheet > 70V9159L9BFGI8

70V9159L9BFGI8

更新时间： 2022-12-29 20:46:23

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	205K
描述
HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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70V9159L9BFGI8 数据手册

IDT70V9169/59L

High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)⁽³⁾

tCYC2

tCH2

tCL2

CLK

CE0

tHC

CE1

tSW tHW

R/W

tSW tHW

(4)

An + 3

An + 4

An +1

An + 2

ADDRESS

tSA

tHA

tSD

DATAIN

Dn + 2

(1)

tCKLZ

(1)

tCD2

(2)

tCKHZ

Qn + 3

DATAOUT

READ

NOP⁽⁵⁾

WRITE

READ

5655 drw 11

Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)⁽³⁾

CYC2

tCH2

tCL2

CLK

CE0

tSC

tHC

CE1

tSW tHW

R/W

tSW tHW

(4)

An + 4

An +1

An + 2

An + 3

Dn + 3

An + 5

ADDRESS

tHA

DATAIN

Dn + 2

(1)

CKLZ

tCD2

(2)

Qn + 4

DATAOUT

(1)

OHZ

READ

WRITE

READ

5655 drw 12

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".

4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

6.42

1...8 9 101112 13 14...16

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