IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) ( VDD= 3.3V ± 0.3V, TA = 0°C to +70°C)
70V9169/59L6
Com'l Only
70V9169/59L7
Com'l & Ind
70V9169/59L9
Com'l Only
Symbol
Parameter
Min.
19
Max.
Min.
22
Max.
Min.
25
15
12
12
6
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CYC1
CYC2
CH1
CL 1
CH2
CL 2
Clock Cycle Time (Flow-Through)(2)
Clock Cycle Time (Pipelined)(2)
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(2)
Clock Rise Time
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
10
12
t
6.5
6.5
4
7.5
7.5
5
t
t
t
4
5
6
____
____
____
tR
3
3
3
____
____
____
tF
Clock Fall Time
3
3
3
____
____
____
t
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HA D
SCN
HCN
SRST
HRST
OE
OLZ
OHZ
CD1
CD2
DC
CKHZ
CKLZ
Address Setup Time
3.5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
Address Hold Time
t
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
3.5
0
t
t
3.5
0
t
t
3.5
0
t
R/W Hold Time
t
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
3.5
0
t
t
3.5
0
t
ADS Hold Time
t
3.5
0
CNTEN Setup Time
t
CNTEN Hold Time
t
3.5
CNTRST Setup Time
t
0
0
1
CNTRST Hold Time
____
____
____
t
Output Enable to Data Valid
6.5
7.5
9
(1)
____
____
____
t
Output Enable to Output Low-Z
2
2
2
t
Output Enable to Output High-Z(1)
Clock to Data Valid (Flow-Through)(2)
Clock to Data Valid (Pipelined)(2)
Data Output Hold After Clock High
1
7
1
7
1
7
____
____
____
t
15
18
20
____
____
____
t
6.5
7.5
9
____
____
____
t
2
2
2
2
2
2
2
2
2
(1)
t
Clock High to Output High-Z
9
9
9
(1)
____
____
____
t
Clock High to Output Low-Z
Port-to-Port Delay
____
____
____
____
____
____
t
CWDD
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
24
9
28
10
35
15
ns
tCCS
ns
5655 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply
when FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER, and FT/PIPEL.
6.482
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