IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VDD = 3.3V ± 0.3, TA = 0°C to +70°C)
70V9089/79X6
Com'l Only
70V9089/79X7
Com'l Only
70V9089/79X9
Com'l Only
Symbol
Parameter
Clock Cycle Time (Flow-Through)(2)
Min.
19
Max.
Min.
22
Max.
Min.
25
15
12
12
6
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYC1
Clock Cycle Time (Pipelined)(2)
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(2)
Clock Rise Time
10
12
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
CYC2
CH1
CL1
CH2
CL2
R
6.5
6.5
4
7.5
7.5
5
4
5
6
____
____
____
3
3
3
____
____
____
F
Clock Fall Time
3
3
3
____
____
____
SA
Address Setup Time
3.5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
HA
Address Hold Time
SC
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
3.5
0
HC
SW
3.5
0
HW
SD
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
3.5
0
HD
SAD
HAD
SCN
HCN
SRST
HRST
OE
3.5
0
ADS Hold Time
3.5
0
CNTEN Setup Time
CNTEN Hold Time
3.5
CNTRST Setup Time
0
0
1
CNTRST Hold Time
____
____
____
Output Enable to Data Valid
Output Enable to Output Low-Z(1)
Output Enable to Output High-Z(1)
Clock to Data Valid (Flow-Through)(2)
Clock to Data Valid (Pipelined)(2)
Data Output Hold After Clock High
Clock High to Output High-Z(1)
Clock High to Output Low-Z(1)
6.5
7.5
9
____
____
____
OLZ
OHZ
CD1
CD2
DC
2
2
2
1
7
1
7
1
7
____
____
____
15
18
20
____
____
____
6.5
7.5
9
____
____
____
2
2
2
2
2
2
2
2
2
CKHZ
CKLZ
9
9
9
____
____
____
Port-to-Port Delay
____
____
____
____
____
____
t
t
CWDD
CCS
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
24
9
28
10
35
15
ns
ns
3750 tbl 11a
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
This parameter is guaranteed by device characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
8
6.42
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