Datasheet > 70V7599S133BFG8

70V7599S133BFG8

更新时间： 2024-02-11 10:08:17

品牌	Logo	应用领域
艾迪悌 - IDT		时钟静态存储器内存集成电路
页数	文件大小	规格书
22页	748K
描述
Dual-Port SRAM, 128KX36, 4.2ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GREEN, FPBGA-208

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70V7599S133BFG8 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	BGA, BGA208,17X17,32	Reach Compliance Code：	compliant
HTS代码：	8542.32.00.41	风险等级：	5.74
最长访问时间：	4.2 ns	其他特性：	PIPELINED OR FLOW THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：	133 MHz	I/O 类型：	COMMON
JESD-30 代码：	S-PBGA-B208	内存密度：	4718592 bit
内存集成电路类型：	DUAL-PORT SRAM	内存宽度：	36
功能数量：	1	端口数量：	2
端子数量：	208	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	128KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA208,17X17,32	封装形状：	SQUARE
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
最大待机电流：	0.03 A	最小待机电流：	3.15 V
子类别：	SRAMs	最大压摆率：	0.645 mA
最大供电电压 (Vsup)：	3.45 V	最小供电电压 (Vsup)：	3.15 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	Base Number Matches：	1

70V7599S133BFG8 数据手册

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

PinNames

Left Port

Right Port

Names

Chip Enables

CE0L

CE1L

CE0R, CE1R

R/W

BA0L - BA5L

0L - A10L

I/O0L - I/O35L

CLK

PL/FT

ADS

CNTEN

REPEAT

BE0L - BE3L

R/W

BA0R - BA5R

0R - A10R

I/O0R - I/O35R

CLK

PL/FT

ADS

CNTEN

REPEAT

BE0R - BE3R

Read/Write Enable

Output Enable

Bank Address⁽⁴⁾

Address

Data Input/Output

Clock

Pipeline/Flow-Through

Address Strobe Enable

Counter Enable

Counter Repeat⁽³⁾

Byte Enables (9-bit bytes)

Power (I/O Bus) (3.3V or 2.5V)⁽¹⁾

NOTES:

1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that

port's I/Os and address controls will operate at 2.5V levels and VDDQX must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

DDQL

DDQR

(1,2)

OPT

OPTR

Option for selecting VDDQX

Power (3.3V)⁽¹⁾

Ground (0V)

3. When REPEATX is asserted, the counter will reset to the last valid address loaded

via ADSX.

TDI

TDO

TCK

Test Data Input

4. Accesses by the ports into specific banks are controlled by the bank address

pins under the user's direct control: each port can access any bank of memory

with the shared array that is not currently being accessed by the opposite port

(i.e., BA0L - BA5L ≠ BA0R - BA5R). In the event that both ports try to access the

same bank at the same time, neither access will be valid, and data at the two

specific addresses targeted by the ports within that bank may be corrupted (in

the case that either or both ports are writing) or may result in invalid output (in

the case that both ports are trying to read).

Test Data Output

Test Logic Clock (10MHz)

Test Mode Select

Reset (Initialize TAP Controller)

TMS

TRST

5626 tbl 01

6.42

1 2 3 456 7 8...22

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与70V7599S133BFG8相关器件

型号	品牌	描述	获取价格	数据表
70V7599S133BFGI	IDT	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM	获取价格
70V7599S133BFGI8	IDT	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM	获取价格
70V7599S133BFI	IDT	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.	获取价格
70V7599S133DR	IDT	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.	获取价格
70V7599S133DRG	IDT	暂无描述	获取价格
70V7599S133DRG8	IDT	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM	获取价格

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