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70V7519S166BFI

更新时间： 2024-02-25 10:36:44

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	226K
描述
HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

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70V7519S166BFI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	PQFP
包装说明：	PLASTIC, QFP-208	针数：	208
Reach Compliance Code：	not_compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.29
Is Samacsys：	N	最长访问时间：	12 ns
其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	166 MHz
I/O 类型：	COMMON	JESD-30 代码：	S-PQFP-G208
JESD-609代码：	e0	长度：	28 mm
内存密度：	9437184 bit	内存集成电路类型：	DUAL-PORT SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端口数量：	2
端子数量：	208	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	256KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装等效代码：	QFP208,1.2SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	4.1 mm
最大待机电流：	0.04 A	最小待机电流：	3.15 V
子类别：	SRAMs	最大压摆率：	0.83 mA
最大供电电压 (Vsup)：	3.45 V	最小供电电压 (Vsup)：	3.15 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	28 mm
Base Number Matches：	1

70V7519S166BFI 数据手册

IDT70V7519S

High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

interface. Registered inputs provide minimal setup and hold times on

address,dataandallcriticalcontrolinputs.

FunctionalDescription

The IDT70V7519 is a high-speed 256Kx36 (9 Mbit) synchronous

Bank-Switchable Dual-Ported SRAM organized into 64 independent

4Kx36banks.BasedonastandardSRAMcoreinsteadofatraditionaltrue

dual-portmemorycore,thisbank-switchabledeviceoffersthebenefitsof

increased density and lower cost-per-bit while retaining many of the

featuresoftruedual-ports.Thesefeaturesincludesimultaneous,random

accesstothesharedarray,separateclocksperport,166MHzoperating

speed,full-boundarycounters,andpinoutscompatiblewiththeIDT70V3599

(128Kx36)dual-portfamily.

An asynchronous output enable is provided to ease asynchronous

bus interfacing. Counter enable inputs are also provided to stall the

operationoftheaddresscountersforfastinterleavedmemoryapplications.

AHIGHonCE⁰oraLOWonCE1foroneclockcyclewillpowerdown

theinternalcircuitryoneachport(individuallycontrolled)toreducestatic

powerconsumption.Dualchipenablesalloweasierbankingofmultiple

IDT70V7519s for depth expansion configurations. Two cycles are

requiredwithCE⁰LOWandCE1HIGHtoreadvaliddataontheoutputs.

Thetwoportsarepermittedindependent,simultaneousaccessinto

separatebankswithinthesharedarray.Accessbytheportsintospecific

banks are controlled by the bank address pins under the user's direct

Depth and Width Expansion

The IDT70V7519 features dual chip enables (refer to Truth

control:eachportcanaccessanybankofmemorywiththesharedarray Table I) in order to facilitate rapid and simple depth expansion with no

thatisnotcurrentlybeingaccessedbytheoppositeport(i.e.,BA0L -BA5L requirements for external logic. Figure 4 illustrates how to control the

≠BA0R-BA5R).Intheeventthatbothportstrytoaccessthesamebank various chip enables in order to expand two devices in depth.

atthesametime,neitheraccesswillbevalid,anddataatthetwospecific

TheIDT70V7519canalsobeusedinapplicationsrequiringexpanded

addressestargetedbytheportswithinthatbankmaybecorrupted(inthe width,asindicatedinFigure4.Throughcombiningthecontrolsignals,the

casethateitherorbothportsarewriting)ormayresultininvalidoutput(in devices can be grouped as necessary to accommodate applications

the case thatbothports are tryingtoread).

needing 72-bits or wider.

TheIDT70V7519providesatruesynchronousDual-PortStaticRAM

(1)

BA6

IDT70V7519

CE0

CE1

VDD

Control Inputs

IDT70V7519

CE1

CE0

BE,

R/W,

Control Inputs

OE,

CLK,

ADS,

REPEAT,

CNTEN

5618 drw 20

Figure 4. Depth and Width Expansion with IDT70V7519

NOTE:

In the case of depth expansion, the additional address pin logically serves as an extension of the bank address. Accesses by the ports into specific banks are

controlled by the bank address pins under the user's direct control: each port can access any bank of memory within the shared array that is not currently

being accessed by the opposite port (i.e., BA^0L- BA6L ≠ BA0R - BA6R). In the event that both ports try to access the same bank at the same time, neither

access will be valid, and data at the two specific addresses targeted by the parts within that bank may be corrupted (in the case that either or both parts are

writing) or may result in invalid output (in the case that both ports are trying to read).

6.42

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与70V7519S166BFI相关器件

型号	品牌	描述	获取价格	数据表
70V7519S166DR	IDT	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.	获取价格
70V7519S166DRG	IDT	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM	获取价格
70V7519S166DRG8	IDT	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM	获取价格
70V7519S166DRGI	IDT	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM	获取价格
70V7519S166DRGI8	IDT	Dual-Port SRAM, 256KX36, 3.6ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM HEIGHT, GREEN, PLASTIC,	获取价格
70V7519S166DRI	IDT	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.	获取价格

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