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70V7519S133BFG8 PDF预览

70V7519S133BFG8

更新时间: 2024-02-20 16:50:18
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 749K
描述
Dual-Port SRAM, 256KX36, 4.2ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GREEN, FPBGA-208

70V7519S133BFG8 技术参数

生命周期:Active包装说明:BGA,
Reach Compliance Code:compliantHTS代码:8542.32.00.41
风险等级:5.7最长访问时间:4.2 ns
其他特性:PIPELINED OR FLOW THROUGH ARCHITECTUREJESD-30 代码:S-PBGA-B208
内存密度:9437184 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:36功能数量:1
端子数量:208字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX36封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
最大供电电压 (Vsup):3.45 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子位置:BOTTOM
Base Number Matches:1

70V7519S133BFG8 数据手册

 浏览型号70V7519S133BFG8的Datasheet PDF文件第5页浏览型号70V7519S133BFG8的Datasheet PDF文件第6页浏览型号70V7519S133BFG8的Datasheet PDF文件第7页浏览型号70V7519S133BFG8的Datasheet PDF文件第9页浏览型号70V7519S133BFG8的Datasheet PDF文件第10页浏览型号70V7519S133BFG8的Datasheet PDF文件第11页 
IDT70V7519S  
High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM  
Industrial and Commercial Temperature Ranges  
Capacitance(1)  
(TA = +25°C, F = 1.0MHZ) PQFP ONLY  
Symbol  
Parameter  
Input Capacitance  
Output Capacitance  
Conditions(2)  
IN = 3dV  
OUT = 3dV  
Max. Unit  
CIN  
V
8
pF  
(3)  
C
OUT  
V
10.5  
pF  
5618 tbl 07  
NOTES:  
1. These parameters are determined by device characterization, but are not  
production tested.  
2. 3dV references the interpolated capacitance when the input and output switch  
from 0V to 3V or from 3V to 0V.  
3. COUT also references CI/O.  
DC Electrical Characteristics Over the Operating  
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)  
70V7519S  
Symbol  
|ILI  
|ILO  
Parameter  
Input Leakage Current(1)  
Output Leakage Current(1)  
Test Conditions  
DDQ = Max., VIN = 0V to VDDQ  
CE = VIH or CE = VIL, VOUT = 0V to VDDQ  
OL = +4mA, VDDQ = Min.  
OH = -4mA, VDDQ = Min.  
OL = +2mA, VDDQ = Min.  
OH = -2mA, VDDQ = Min.  
Min.  
Max.  
10  
Unit  
µA  
µA  
V
___  
___  
___  
|
V
|
10  
0
1
V
OL (3.3V) Output Low Voltage(2)  
OH (3.3V) Output High Voltage(2)  
OL (2.5V) Output Low Voltage(2)  
OH (2.5V) Output High Voltage(2)  
I
0.4  
___  
V
I
2.4  
___  
V
V
I
0.4  
___  
V
V
I
2.0  
V
5618 tbl 08  
NOTES:  
1. At VDD < 2.0V leakages are undefined.  
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.  
6.42  
8

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