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70V7519S133BFG8

更新时间： 2024-01-30 04:16:24
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 749K
描述
Dual-Port SRAM, 256KX36, 4.2ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GREEN, FPBGA-208

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70V7519S133BFG8 技术参数

生命周期：Active包装说明：BGA,
Reach Compliance Code：compliantHTS代码：8542.32.00.41
风险等级：5.7最长访问时间：4.2 ns
其他特性：PIPELINED OR FLOW THROUGH ARCHITECTUREJESD-30 代码：S-PBGA-B208
内存密度：9437184 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：36功能数量：1
端子数量：208字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX36封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY并行/串行：PARALLEL
最大供电电压 (Vsup)：3.45 V最小供电电压 (Vsup)：3.15 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：BALL端子位置：BOTTOM
Base Number Matches：1

70V7519S133BFG8 数据手册

 浏览型号70V7519S133BFG8的Datasheet PDF文件第3页浏览型号70V7519S133BFG8的Datasheet PDF文件第4页浏览型号70V7519S133BFG8的Datasheet PDF文件第5页浏览型号70V7519S133BFG8的Datasheet PDF文件第7页浏览型号70V7519S133BFG8的Datasheet PDF文件第8页浏览型号70V7519S133BFG8的Datasheet PDF文件第9页 
IDT70V7519S  
High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM  
Industrial and Commercial Temperature Ranges  
Truth Table I—Read/Write and Enable Control(1,2,3,4)  
Byte 3  
I/O27-35  
Byte 2  
I/O18-26  
Byte 1  
I/O9-17  
Byte 0  
I/O0-8  
OE3  
CLK  
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
CE  
X
1
R/W  
X
X
X
L
MODE  
CE  
0
BE  
3
BE  
2
BE  
1
BE0  
X
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
H
H
H
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z Deselected–Power Down  
High-Z Deselected–Power Down  
High-Z All Bytes Deselected  
X
L
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
DIN  
Write to Byte 0 Only  
X
H
H
H
L
L
DIN  
High-Z Write to Byte 1 Only  
High-Z Write to Byte 2 Only  
High-Z Write to Byte 3 Only  
X
H
H
L
L
DIN  
High-Z  
High-Z  
X
H
H
L
L
DIN  
High-Z  
High-Z  
X
H
L
L
High-Z  
DIN  
DIN  
Write to Lower 2 Bytes Only  
X
H
L
H
L
L
DIN  
DIN  
High-Z  
High-Z Write to Upper 2 bytes Only  
X
L
L
L
DIN  
DIN  
DIN  
DIN  
Write to All Bytes  
Read Byte 0 Only  
L
H
H
H
L
H
H
L
H
L
L
H
H
H
H
H
H
H
X
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
DOUT  
L
H
H
H
L
DOUT  
High-Z Read Byte 1 Only  
High-Z Read Byte 2 Only  
High-Z Read Byte 3 Only  
L
H
H
L
DOUT  
High-Z  
High-Z  
L
H
H
L
DOUT  
High-Z  
High-Z  
L
H
L
High-Z  
DOUT  
DOUT  
Read Lower 2 Bytes Only  
High-Z Read Upper 2 Bytes Only  
Read All Bytes  
High-Z Outputs Disabled  
L
H
L
H
L
DOUT  
DOUT  
High-Z  
L
H
L
L
DOUT  
DOUT  
DOUT  
DOUT  
X
X
X
X
High-Z  
High-Z  
High-Z  
5618 tbl 02  
NOTES:  
1. "H" = VIH, "L" = VIL, "X" = Don't Care.  
2. ADS, CNTEN, REPEAT are set as appropriate for address access. Refer to Truth Table II for details.  
3. OE is an asynchronous input signal.  
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.  
Truth Table II—Address and Address Counter Control(1,2,7)  
Previous  
Address  
Addr  
Used  
Address  
CLK  
↑
I/O(3)  
I/O (n) External Address Used  
I/O(n+1) Counter Enabled—Internal Address generation  
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)  
I/O(0) Counter Set to last valid ADS load  
MODE  
ADS CNTEN REPEAT(6)  
An  
X
X
An  
An  
L(4)  
H
X
L(5)  
H
H
D
An + 1  
An + 1  
An  
D
D
↑
X
An + 1  
X
H
H
H
↑
X
X
X
L(4)  
D
↑
5618 tbl 03  
NOTES:  
1. "H" = VIH, "L" = VIL, "X" = Don't Care.  
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.  
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.  
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn  
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.  
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded  
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.  
7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address  
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer  
to Timing Waveform of Counter Repeat, page 18. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA0L  
- BA5L ≠ BA0R - BA5R), as this condition will invalidate the access for both ports. Please refer to the functional description on page 19 for details.  
6.42  
6
1...3456789...22

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