IDT70V7319S
High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V7319 is a high-speed 256Kx18 (4Mbit) synchronous
Bank-Switchable Dual-Ported SRAM organized into 64 independent
4Kx18 banks. The device has two independent ports with separate
control,address,andI/Opinsforeachport,allowingeachporttoaccess
any 4Kx18 memory block not already accessed by the other port.
Accesses by the ports into specific banks are controlled via the bank
addresspinsundertheuser'sdirectcontrol.
register, the IDT70V7319 has been optimized for applications having
unidirectional or bidirectional data flow in bursts. An automatic power
downfeature,controlledbyCE0andCE1,permitstheon-chipcircuitryof
each porttoenteraverylowstandbypowermode.Thedualchipenables
alsofacilitatedepthexpansion.
The70V7319cansupportanoperatingvoltageofeither3.3Vor2.5V
ononeorbothports,controllablebytheOPTpins.Thepowersupplyfor
the core of the device(VDD) remains at 3.3V. Please refer also to the
functionaldescriptiononpage18.
Registersoncontrol,data,andaddressinputsprovideminimalsetup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times. With an input data
PinConfiguration(1,2,3,4)
A1
IO9L
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A17
A4
A5
A10
A15
A16
NC
V
SS
BA4L BA0L
A
8L
NC
CLK
L
CNTEN
L
A
4L
A
0L
VSS
TDO NC
V
DD
OPT
L
NC
B1
B2
B3
B6
BA1L
B7
B9
CE0L
B11
B12
B13
B17
B4
B5
B8
B10
B14
B15
B16
NC
V
SS
NC
A
9L
ADS
L
A
5L
A
1L
NC
TDI BA5L
NC
VSS
VSS
VDDQR I/O8L
C1
C6
BA2L
C2
C3
C4
C5
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
C17
VDDQL
I/O9R
VDDQR PL/FT
L
NC
A
10L
UB
L
CE1L
V
SS R/W
L
A
6L
3L
A
2L
NC
VDD I/O8R
VSS
D1
D2
D6
D9
D11
REPEATL
D3
D5
BA3L
D7
D8
D10
D12
D13
D14
D15
D16
D17
D4
NC
V
SS
A11L
V
DD
I/O10L
A
7L
LB
L
OE
L
A
V
DD
NC
V
DDQL I/O7L I/O7R
NC
E1
E2
E3
E4
E14
E16
E17
E15
I/O11L NC
V
DDQR I/O10R
I/O6L
VSS
NC
NC
F1
F2
F3
F14
F15
F16
F17
F4
VDDQL I/O11R NC
V
SS I/O6R NC
VDDQR
V
SS
G1
G2
G4
G14
G15
G16
G3
G17
NC
VSS
NC
NC
VDDQL I/O5L
I/O12L
NC
H3
H4
H1
H2
H16
H17
H14
H15
70V7319BF
BF-208(5)
V
DDQR I/O12R
V
DD
NC
V
SS I/O5R
V
DD
NC
J1
DDQL
J2
J3 J4
J14
J15
J16
J17
V
V
DD
V
SS
V
SS
V
SS
V
DD
VSS
VDDQR
208-Pin fpBGA
Top View(6)
K2
K4
K15
K16
K1
K3
K14
K17
V
SS
V
SS
VDDQL I/O4R
I/O3R
I/O14R
I/O13R
VSS
L3
L4
L15
L16
L17
L1
L2
L14
VDDQR I/O13L
I/O3L
V
SS I/O4L
NC I/O14L
NC
M1
M2
M3
M4
M16
M17
M14
SS
M15
VDDQL NC I/O15R
V
SS
I/O2R
VDDQR
V
NC
N16
N17
N4
N15
N1
N2
N3
N14
NC
I/O2L
I/O15L
VDDQL
NC
VSS
NC
I/O1R
P1
P2
P3
P4
P5
P7
BA0R
P8
P9
P10
P11
P12
P14
P15
P16
P17
P6
P13
I/O16R I/O16L
VDDQR NC TRST
A
8R
NC
V
DD CLK
R
CNTEN
R
NC I/O1L
V
SS
NC
BA4R
A4R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R17
R15
BA5R BA1R
A
9R
NC CE0R
V
SS ADS
R
I/O0R
V
SS
NC I/O17R TCK
A5R
A
1R
VSS
VDDQR
VDDQL
T2
T3
T1
T4
T5
T8
T9
CE1R
T15
T16
T17
T6
BA2R
T7
T10
T11
T12
T13
T14
I/O17L
VDDQL
NC
TMS NC
UB
R
NC
VSS
NC
A
10R
V
SS R/W
R
A
6R
A2R
VSS
U1
U2
U3
U4
U5
U6
U7
U17
U8
U9
U10
U11
REPEAT
U12
U13
U14
DD
U16
U15
V
SS
NC PL/FT
R
NC BA3R
A
11R
A
7R
I/O0L
LB
R
V
DD
OE
R
R
A3R
A
0R
V
NC
OPT
R
5629 drw 02c
NOTES:
1. AllVDD pinsmustbeconnectedto3.3Vpowersupply.
2. AllVDDQ pinsmustbeconnectedtoappropriatepowersupply:3.3VifOPTpinforthatportissettoVIH (3.3V),and2.5VifOPTpinforthatportis
settoVIL (0V).
3. AllVSSpinsmustbeconnectedtogroundsupply.
4. Packagebodyisapproximately15mmx15mmx1.4mmwith0.8mmballpitch.
5. Thispackagecodeisusedtoreferencethepackagediagram.
6. Thistextdoesnotindicateorientationoftheactualpart-marking.
6.42
2