HIGH-SPEED 3.3V 256K x 18
SYNCHRONOUS
IDT70V7319S
BANK-SWITCHABLE
DUAL-PORTSTATICRAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆
256K x 18 Synchronous Bank-Switchable Dual-ported SRAM
Architecture
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MH
– 64 independent 4K x 18 banks
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus match-
ingcompatibility
– 4 megabits of memory on chip
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◆
◆
◆
◆
Bank access controlled via bank address pins
High-speed data access
– Commercial:3.4ns(200MHz)/3.6ns(166MHz)/
4.2ns(133MHz)(max.)
LVTTL- compatible, 3.3V (±150mV) power supply
for core
– Industrial:3.6ns(166MHz)/4.2ns(133MHz)(max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additionallogic
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on each
port
◆
◆
◆
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Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
◆
Full synchronous operation on both ports
– 5nscycletime, 200MHzoperation(14Gbpsbandwidth)
– Fast 3.4ns clock to data out
Available in a 208-pin fine pitch Ball Grid Array (fpBGA) and
256-pin Ball Grid Array (BGA)
◆
◆
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
FunctionalBlockDiagram
PL/FT
L
PL/FT
OPT
CLK
ADS
CNTEN
REPEAT
R/W
R
OPT
L
R
CLK
ADS
CNTEN
L
L
L
R
R
R
REPEAT
L
R
R/W
CE0L
CE1L
L
R
MUX
CONTROL
LOGIC
CONTROL
LOGIC
CE0R
CE1R
4Kx18
MEMORY
ARRAY
UB
LB
OE
L
L
L
UB
LB
OE
R
R
R
(BANK 0)
MUX
MUX
I/O
CONTROL
I/O
CONTROL
I/O0L-17L
I/O0R-17R
4Kx18
MEMORY
ARRAY
A
11R
0R
(BANK 1)
A
11L
ADDRESS
DECODE
ADDRESS
DECODE
A
A
0L
MUX
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
BANK
DECODE
BANK
DECODE
MUX
4Kx18
MEMORY
ARRAY
(BANK 63)
NOTE:
MUX
1. TheBank-Switchabledual-portusesatrueSRAMcore
insteadofthetraditionaldual-portSRAMcore.Asaresult,it
hasuniqueoperatingcharacteristics.Pleaserefertothe
functionaldescriptiononpage19fordetails.
,
5629 drw 01
TMS
TCK
TRST
TDI
TDO
JTAG
JUNE 2015
1
DSC 5629/10
©2015 Integrated Device Technology, Inc.