5秒后页面跳转
70V261L55PFGI PDF预览

70V261L55PFGI

更新时间: 2022-02-26 09:01:06
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
17页 338K
描述
HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM

70V261L55PFGI 数据手册

 浏览型号70V261L55PFGI的Datasheet PDF文件第4页浏览型号70V261L55PFGI的Datasheet PDF文件第5页浏览型号70V261L55PFGI的Datasheet PDF文件第6页浏览型号70V261L55PFGI的Datasheet PDF文件第8页浏览型号70V261L55PFGI的Datasheet PDF文件第9页浏览型号70V261L55PFGI的Datasheet PDF文件第10页 
IDT70V261S/L  
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt  
Industrial and Commercial Temperature Ranges  
Waveform of Read Cycles(5)  
tRC  
ADDR  
(4)  
t
t
AA  
(4)  
ACE  
CE  
OE  
(4)  
t
AOE  
(4)  
t
ABE  
UB, LB  
R/W  
(1)  
tOH  
tLZ  
VALID DATA(4)  
DATAOUT  
BUSYOUT  
(2)  
tHZ  
(3,4)  
3040 drw 0  
tBDD  
NOTES:  
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.  
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.  
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no  
relation to valid output data.  
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.  
5. SEM = VIH.  
AC Electrical Characteristics Over the  
OperatingTemperatureandSupplyVoltage(5)  
70V261X25  
70V261X35  
Com'l Only  
70V261X55  
Com'l Only  
Com'l  
& Ind  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
WRI TE CYCLE  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
t
WC  
EW  
AW  
AS  
WP  
WR  
DW  
HZ  
DH  
WZ  
OW  
SWRD  
SPS  
Write Cycle Time  
25  
20  
20  
0
35  
30  
30  
0
55  
45  
45  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
Chip Enable to End-of-Write(3)  
Address Valid to End-of-Write  
Address Set-up Time(3)  
Write Pulse Width  
t
t
t
20  
0
25  
0
40  
0
t
Write Recovery Time  
Data Valid to End-of-Write  
Output High-Z Time(1,2)  
Data Hold Time(4)  
t
15  
20  
30  
____  
____  
____  
t
15  
20  
25  
____  
____  
____  
t
0
0
0
Write Enable to Output in High-Z(1,2)  
Output Active from End-of-Write(1, 2,4)  
SEM Flag Write to Read Time  
SEM Flag Contention Window  
15  
20  
25  
____  
____  
____  
t
____  
____  
____  
t
0
5
5
0
5
5
0
5
5
____  
____  
____  
____  
____  
____  
t
t
ns  
3040 tbl 12  
NOTES:  
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).  
2. This parameter is guaranteed by device characterization, but is not production tested.  
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.  
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and  
temperature, the actual tDH will always be smaller than the actual tOW.  
5. 'X' in part number indicates power rating (S or L).  
7
6.42  

与70V261L55PFGI相关器件

型号 品牌 描述 获取价格 数据表
70V261L55PFGI8 IDT HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM

获取价格

70V261S25PF8 IDT TQFP-100, Reel

获取价格

70V261S25PFG IDT Dual-Port SRAM, 16KX16, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, T

获取价格

70V261S25PFG8 IDT Dual-Port SRAM, 16KX16, 25ns, CMOS, PQFP100

获取价格

70V261S25PFGI IDT HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM

获取价格

70V261S25PFGI8 IDT HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM

获取价格