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709179S15PF PDF预览

709179S15PF

更新时间: 2024-02-25 08:33:31
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
15页 179K
描述
TQFP-100, Tray

709179S15PF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP-100针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:18 nsJESD-30 代码:S-PQFP-G100
JESD-609代码:e3长度:14 mm
内存密度:294912 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:9湿度敏感等级:3
功能数量:1端子数量:100
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX9
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

709179S15PF 数据手册

 浏览型号709179S15PF的Datasheet PDF文件第5页浏览型号709179S15PF的Datasheet PDF文件第6页浏览型号709179S15PF的Datasheet PDF文件第7页浏览型号709179S15PF的Datasheet PDF文件第9页浏览型号709179S15PF的Datasheet PDF文件第10页浏览型号709179S15PF的Datasheet PDF文件第11页 
Preliminary  
IDT709179L  
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM  
Industrial and Commercial Temperature Ranges  
Timing Waveform of Read Cycle for  
ꢀlow-Through Output (FT/PIPE"X" = VIL)(3,6)  
tCYC1  
tCH1  
tCL1  
CLK  
CE0  
tSC  
tHC  
tSC  
tHC  
CE1  
R/W  
tHW  
tHA  
tSW  
tSA  
ADDRESS(5)  
DATAOUT  
An  
An + 1  
An + 2  
An + 3  
(1)  
tDC  
tCD1  
tCKHZ  
Qn  
Qn + 1  
Qn + 2  
(1)  
(1)  
tCKLZ  
tDC  
(1)  
tOHZ  
tOLZ  
tOE  
OE(2)  
5644 drw 07  
Timing Waveform of Read Cycle for Pipelined Operation  
(FT/PIPE"X" = VIH)(3,6)  
t
CYC2  
t
CH2  
t
CL2  
CLK  
CE  
0
t
SC  
t
HC  
t
SC  
t
HC  
(4)  
CE  
1
R/W  
t
HW  
t
SW  
t
SA  
t
HA  
ADDRESS(5)  
An  
An + 1  
An + 2  
Qn  
An + 3  
(1 Latency)  
t
DC  
t
CD2  
Qn + 2 (6)  
DATAOUT  
Qn + 1  
(1)  
t
CKLZ  
(1)  
(1)  
t
OHZ  
t
OLZ  
OE(2)  
t
OE  
5644 drw 08  
NOTES:  
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).  
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.  
3. ADS = VIL, CNTEN and CNTRST = VIH.  
4. The output is disabled (High-Impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock. Refer to Truth Table 1.  
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers  
are for reference use only.  
6. "X" here denotes Left or Right port. The diagram is with respect to that port.  
8
6.42  

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