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709179S15PF PDF预览

709179S15PF

更新时间: 2024-01-03 05:56:28
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
15页 179K
描述
TQFP-100, Tray

709179S15PF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP-100针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:18 nsJESD-30 代码:S-PQFP-G100
JESD-609代码:e3长度:14 mm
内存密度:294912 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:9湿度敏感等级:3
功能数量:1端子数量:100
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX9
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

709179S15PF 数据手册

 浏览型号709179S15PF的Datasheet PDF文件第2页浏览型号709179S15PF的Datasheet PDF文件第3页浏览型号709179S15PF的Datasheet PDF文件第4页浏览型号709179S15PF的Datasheet PDF文件第6页浏览型号709179S15PF的Datasheet PDF文件第7页浏览型号709179S15PF的Datasheet PDF文件第8页 
Preliminary  
IDT709179L  
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM  
Industrial and Commercial Temperature Ranges  
DC Electrical Characteristics Over the Operating  
Temperature and Supply Voltage Range(3) (VCC = 5V ± 10%)  
709179L7  
Com'l Only  
709179L9  
Com'l  
& Ind  
709179L12  
Com'l Only  
Symbol  
Parameter  
Test Condition  
Version  
COM'L  
Typ.(4)  
Max.  
Typ.(4)  
Max.  
400  
430  
135  
160  
275  
295  
Typ.(4)  
Max.  
Unit  
CC  
I
Dynamic Operating  
Current  
(Both Ports Active)  
mA  
L
L
L
L
L
L
275  
465  
250  
250  
80  
230  
355  
CEL and CER= VIL  
Outputs Disabled  
(1)  
____  
____  
____  
____  
IND  
f = fMAX  
ISB1  
ISB2  
Standby Current  
(Both Ports - TTL  
Level Inputs)  
COM'L  
IND  
95  
150  
70  
110  
mA  
mA  
CEL = CER = VIH  
(1)  
f = fMAX  
____  
____  
____  
____  
80  
Standby Current  
(One Port - TTL  
Level Inputs)  
COM'L  
IND  
200  
295  
175  
175  
150  
240  
CE  
CE"AB" == VVIIHL and  
(3)  
____  
____  
____  
____  
Active Port Outputs  
(1)  
Disabled, f=fMAX  
ISB3  
ISB4  
Full Standby Current  
(Both Ports -  
Both Ports CER and  
CEL > VCC - 0.2V  
VIN > VCC - 0.2V or  
VIN < 0.2V, f = 0(2)  
mA  
mA  
COM'L  
IND  
L
L
0.5  
3.0  
0.5  
0.5  
3.0  
6.0  
0.5  
3.0  
____  
____  
____  
____  
CMOS Level Inputs)  
Full Standby Current  
(One Port -  
CMOS Level Inputs)  
COM'L  
IND  
L
L
190  
290  
170  
170  
270  
290  
140  
225  
CE  
CE"AB" >< V0.C2CV -a0n.d2V  
VIN > VCC - 0.2V or  
VIN < 0.2V, Active Port  
(5)  
____  
____  
____  
____  
(1)  
Outputs Disabled, f = fMAX  
5644 tbl 09  
NOTES:  
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of  
GND to 3V.  
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.  
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".  
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).  
5. CEX = VIL means CE0X = VIL and CE1X = VIH  
CEX = VIH means CE0X = VIH or CE1X = VIL  
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V  
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V  
"X" represents "L" for left port or "R" for right port.  
6.542  

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