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7024 PDF预览

7024

更新时间: 2023-12-20 18:44:44
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瑞萨 - RENESAS /
页数 文件大小 规格书
23页 336K
描述
4K x 16 Dual-Port RAM

7024 数据手册

 浏览型号7024的Datasheet PDF文件第14页浏览型号7024的Datasheet PDF文件第15页浏览型号7024的Datasheet PDF文件第16页浏览型号7024的Datasheet PDF文件第18页浏览型号7024的Datasheet PDF文件第19页浏览型号7024的Datasheet PDF文件第20页 
7024S/L  
High-Speed 4K x 16 Dual-Port Static RAM  
Military, Industrial and Commercial Temperature Ranges  
Truth Table IV —  
AddressBUSY Arbitration  
Inputs  
Outputs  
A
0L-A11L  
(1)  
(1)  
A
0R-A11R  
Function  
Normal  
Normal  
Normal  
CE  
L
CE  
R
BUSY  
L
BUSYR  
X
H
X
L
X
X
H
L
NO MATCH  
MATCH  
H
H
H
H
MATCH  
H
H
MATCH  
(2)  
(2)  
Write Inhibit(3)  
2740 tbl 17  
NOTES:  
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7024 are  
push pull, not open drain outputs. On slaves, the BUSY asserted input internally inhibits write.  
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address  
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.  
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored  
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.  
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)  
Functions  
D0  
- D15 Left  
D0  
- D15 Right  
Status  
No Action  
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free  
Left Port Writes "0" to Semaphore  
Right Port Writes "0" to Semaphore  
Left Port Writes "1" to Semaphore  
Left Port Writes "0" to Semaphore  
Right Port Writes "1" to Semaphore  
Left Port Writes "1" to Semaphore  
Right Port Writes "0" to Semaphore  
Right Port Writes "1" to Semaphore  
Left Port Writes "0" to Semaphore  
Left Port Writes "1" to Semaphore  
Left port has semaphore token  
No change. Right side has no write access to semaphore  
Right port obtains semaphore token  
No change. Left port has no write access to semaphore  
Left port obtains semaphore token  
Semaphore free  
Right port has semaphore token  
Semaphore free  
Left port has semaphore token  
Semaphore free  
2740 tbl 18  
NOTES:  
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024.  
2. There are eight semaphore flags written to via I/O0 and read from all the I/O's. These eight semaphores are addressed by A0-A2.  
3. CE = VIH, SEM = VIL, to access the Semaphores. Refer to the Semaphore Read/Write Control Truth Table.  
FunctionalDescription  
TheIDT7024providestwoportswithseparatecontrol,addressand  
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation  
inmemory.TheIDT7024hasanautomaticpowerdownfeaturecontrolled  
by CE. The CE controls on-chip power down circuitry that permits the  
respectiveporttogointoastandbymodewhennotselected(CE=VIH).  
Whenaportisenabled,accesstotheentirememoryarrayispermitted.  
ormessagecenter)isassignedtoeachport. Theleftportinterruptflag  
(INTL) is asserted when the right port writes to memory location FFE  
(HEX), whereawriteisdefinedastheCE=R/W=VILpertheTruthTable  
III.TheleftportclearstheinterruptbyaccessaddresslocationFFEaccess  
when CER = OER = VIL, R/W is a "don't care". Likewise, the right port  
interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation  
FFF(HEX)andtocleartheinterruptflag(INTR),therightportmustaccess  
thememorylocationFFF. Themessage(16bits)atFFEorFFFisuser-  
defined,sinceitisanaddressableSRAMlocation.Iftheinterruptfunction  
Interrupts  
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox  
6.42  
17  
Feb.20.20  

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