Datasheet > 7018VL15PF8

7018VL15PF8

更新时间： 2024-11-16 05:41:19

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
17页	154K
描述
TQFP-100, Reel

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中文翻译

获取价格

技术参数
数据手册

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7018VL15PF8 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	TQFP
包装说明：	,	针数：	100
Reach Compliance Code：	not_compliant	风险等级：	5.84
JESD-609代码：	e0	内存集成电路类型：	DUAL-PORT SRAM
湿度敏感等级：	3	峰值回流温度（摄氏度）：	240
端子面层：	Tin/Lead (Sn/Pb)	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

7018VL15PF8 数据手册

HIGH-SPEED

64K x 9 DUAL-PORT

STATIC RAM

IDT7018L

Features

◆

than one device

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in a 100-pin TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

– Commercial:15/20ns (max.)

– Industrial:20ns (max.)

Low-power operation

◆

– IDT7018L

◆

Active:1W(typ.)

Standby: 1mW (typ.)

Dual chip enables allow for depth expansion without

external logic

IDT7018 easily expands data bus width to 18 bits or

more using the Master/Slave select when cascading more

◆

FunctionalBlockDiagram

R/W

CE0L

CE1L

CE0R

CE1R

OE_L

I/O

Control

I/O

Control

I/O0-8L

I/O_0-8R

(1,2)

BUSY_L

(1,2)

BUSY_R

64Kx9

MEMORY

ARRAY

7018

15L

15R

Address

Decoder

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE0L

CE_0R

R/W

SEM

INTL

SEM

(2)

INT

M/S⁽¹⁾

4841 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S = V^IL) and an output when it is a Master (M/S = VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

NOVEMBER 2001

DSC-4841/3

12 3 4 5 6 7...17

中文翻译

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