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6T39007ANLGI8 PDF预览

6T39007ANLGI8

更新时间: 2024-11-23 06:31:07
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路
页数 文件大小 规格书
15页 279K
描述
CLOCK DISTRIBUTION CIRCUIT

6T39007ANLGI8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:VFQFPN
包装说明:QFN-24针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
Is Samacsys:N系列:9070
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-XQCC-N24
JESD-609代码:e3长度:4 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.004 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:24
实输出次数:6最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC24,.16SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
电源:2.5 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.75 V最小供电电压 (Vsup):2.25 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4 mmBase Number Matches:1

6T39007ANLGI8 数据手册

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DATASHEET  
CLOCK DISTRIBUTION CIRCUIT  
IDT6T39007A  
Description  
Features  
Packaged in 24-pin QFN  
TCXO sine wave input  
+2.5 V operating voltage  
Four buffered LVDS outputs  
The IDT6T39007A is a low-power, four output clock  
distribution circuit. The device takes a TCXO or 1.8 V to  
2.5 V LVCMOS input and generates four high-quality LVDS  
outputs, and two programmable divided outputs.  
It includes a redundant input with automatic glitch-free  
switching when the primary reference is removed. The  
primary input may be selected by the user by pulling the  
SEL pin low or high. If the primary input is removed and  
brought back, it will not be re-selected until 1024 cycles  
have passed.  
Two programmable outputs for power control up to 3.0 V  
LVCMOS levels based on VDDO1/VDDO2  
2
Individual output enables controlled via I C or OEx  
Pb-free, RoHS compliant package  
Industrial temperature range (-40°C to +85°C)  
The IDT6T39007A specifically addresses the needs of  
handheld applications in both performance and package  
size. The device is packaged in a small 4mm x 4mm 24-pin  
QFN, allowing optimal use for limited board space.  
Block Diagram  
VDD 2.5 V  
3
OE1  
SEL  
SCLK  
OUT1 LVDS  
OE2  
OUT2 LVDS  
SDATA  
OUT3 LVDS  
OUT4 LVDS  
LVCMOS_INB  
TCXO_INA  
±100mVpp  
VDDO1  
PWRCTRL_CLK1  
Divide  
Logic  
MUX  
VDDO2  
PWRCTRL_CLK2  
2
GND  
IDT™ CLOCK DISTRIBUTION CIRCUIT  
1
IDT6T39007A REV G 111009  

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