Datasheet > 68HC705L5

68HC705L5

更新时间： 2022-12-19 08:30:28

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
200页	942K
描述
General Release Specification

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数据手册

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68HC705L5 数据手册

Freescale Semiconductor, Inc.

MC68HC705L5

A.15.4 3.3-Volt a nd 5.0-Volt Control Tim ing

(1)

Symbol

Min

Max

Unit

Characteristic

Frequency of oscillation (OSC)

Crystal

External Clock

—

4.2

MHz

OSC

(2)

Internal operating frequency , crystal or external

clock (f /2)

OSC

—

2.1

1.0

MHz

= 4.5 V to 5.5 V

= 3.0 V to 5.5 V

Cycle time (fast OSC selected)

= 4.5 V to 5.5 V

= 3.0 V to 5.5 V

480

1.0

—

µs

cyc

RESET pulse width (when bus clock active)

1.5

—

cyc

Timer

Resolution

Input capture (TCAP) pulse width

4.0

284

—

RESL

, t

cyc

TH TL

Interrupt pulse width low (edge-triggered)

284

see note

110

—

ILIH

(3)

Interrupt pulse period

cyc

ILIL

OSC1 pulse width (external clock input)

, t

OH OL

1. +3.0 ≤ V_DD≤ +5.5 Vdc, V_SS= 0 Vdc,T_L≤ T_A≤ T_H, unless otherwise noted.

2. The system clock divider configuration (SYS1–SYS0 bits) should be selected such that the internal operating frequency (f_OP

does not exceed value specified in f_OPfor a given f_OSC

3. The minimum period, t_ILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine

plus 21 t_cyc

)

MC68HC(7)05L5 — Rev. 2.0

MOTOROLA

General Release Specification

197

MC68HC705L5

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