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651BMLFT

更新时间: 2024-01-04 19:35:21
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 181K
描述
LOW SKEW 1 TO 4 CLOCK BUFFER

651BMLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ActiveReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8536.50.90.65
风险等级:2.23执行器类型:LEVER
其他特性:O.F. = 1.5 NM主体宽度:31.8 mm
主体高度:24 mm主体长度或直径:34.5 mm
触点(交流)最大额定R负载:15A@250VAC最大触点电流(交流):15 A
最大触点电流(直流):15 A触点(直流)最大额定R负载:15A@12VDC
最大触点电压(交流):250 V最大触点电压(直流):12 V
电气寿命:10000 Cycle(s)安装特点:PANEL MOUNT
最高工作温度:55 °C最低工作温度:-20 °C
包装方法:BULK表面贴装:NO
开关动作:LATCHED开关功能:3PST
开关类型:TOGGLE SWITCH端接类型:SCREW
Base Number Matches:1

651BMLFT 数据手册

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ICS651B  
LOW SKEW 1 TO 4 CLOCK BUFFER  
FAN OUT BUFFER  
Pin Assignment  
8
ICLK  
1
OE  
VDD  
Q1  
Q2  
Q3  
2
3
4
7
GND  
Q4  
6
5
Pin Descriptions  
Pin  
Pin  
Pin  
Pin Description  
Number Name Type  
1
2
3
4
5
6
7
8
ICLK  
Q1  
Input  
Clock Input. 3.3 V tolerant input.  
Output Clock Output 1.  
Q2  
Output Clock Output 2.  
Q3  
Output Clock Output 3.  
Q4  
Output Clock Output 4.  
GND  
VDD  
OE  
Power Connect to ground.  
Power Connect to +1.5 V or +2.5 V.  
Input  
Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.  
External Components  
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF  
should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33 series  
terminating resistor may be used on each clock output if the trace is longer than 1 inch.  
To achieve the low output skew that the ICS651B is capable of, careful attention must be paid to board layout.  
Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they  
do not, the output skew will be degraded. For example, using a 30series termination on one output (with 33on  
the others) will cause at least 15 ps of skew.  
IDT™ / ICS™ LOW SKEW 1 TO 4 CLOCK BUFFER  
2
ICS651B  
REV B 112509  

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