Model 633
Very Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Output Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
-
TYP
2
MAX
5
UNIT
ms
Start Up Time
TS
Application of VCC
Enable Function [Standby]
Enable Input Voltage
Disable Input Voltage
Disable Time
VIH
VIL
Pin 1 or 2 Logic '1', Output Enabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '1', Output Enabled
Bandwidth 12 kHz - 20 MHz
-
0.7VCC
-
-
-
V
V
-
-
-
-
-
-
0.3VCC
TPLZ
-
200
ns
ms
fs
Enable Time
TPLZ
-
2
Phase Jitter, RMS
Period Jitter, RMS
Period Jitter, pk-pk
tjrms
pjrms
pjpk-pk
300
2.6
25
500
-
-
ps
ps
-
Enable Truth Table
Pin 1 or Pin 2
Logic ‘1’
Open
Pin 4 & Pin 5
Output
Output
Logic ‘0’
High Imp.
Test Circuit
LVPECL
LVDS
Output Waveform
LVPECL or LVDS
DOC# 008-0578-0 Rev. B
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