Datasheet > 5V2305SPGGK

5V2305SPGGK

更新时间： 2022-02-26 11:05:51

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
10页	126K
描述
High-Performance 1 to 5 Clock Buffer

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数据手册

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5V2305SPGGK 数据手册

5V2305S DATASHEET

AC Electrical Characteristics

(VDD = 1.8V, 2.5V, 3.3V)

VDD = 1.8V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise

Parameter

Input Frequency

Symbol

Conditions

Min. Typ. Max. Units

200

1.0

MHz

Output Rise Time

t_OR

t_OF

t_EN

t_DIS

0.36 to 1.44 V, C_L=5 pF

0.6

Output Fall Time

1.44 to 0.36 V, C_L=5 pF

C_L< 5 pF

Output Enable Time

Output Disable Time

Start-up Time

cycles

C_L< 5 pF

t_START-UPPart start-up time for valid outputs after VDD ramp-up

135MHz, Note 1

Propagation Delay

1.5

2.2

Buffer Additive Phase Jitter, RMS

Output to Output Skew

Device to Device Skew

125MHz, Integration Range: 12kHz-20MHz

Rising edges at VDD/2, Note 2

0.05

500

Rising edges at VDD/2

VDD = 2.5 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise

Parameter

Input Frequency

Symbol

Conditions

Min. Typ. Max. Units

200

1.0

MHz

Output Rise Time

t_OR

t_OF

t_EN

t_DIS

0.5 to 2.0 V, C_L=5 pF

0.6

Output Fall Time

2.0 to 0.5 V, C_L=5 pF

C_L< 5 pF

Output Enable Time

Output Disable Time

Start-up Time

cycles

C_L< 5 pF

t_START-UPPart start-up time for valid outputs after VDD ramp-up

135MHz, Note 1

Propagation Delay

1.8

2.5

4.5

0.05

Buffer Additive Phase Jitter, RMS

Output to Output Skew

Device to Device Skew

125MHz, Integration Range: 12kHz-20MHz

Rising edges at VDD/2, Note 2

Rising edges at VDD/2

500

VDD = 3.3 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise

Parameter

Input Frequency

Symbol

Conditions

Min. Typ. Max. Units

200

1.0

MHz

Output Rise Time

t_OR

t_OF

t_EN

t_DIS

0.66 to 2.64 V, C_L=5 pF

0.6

Output Fall Time

2.64 to 0.66 V, C_L=5 pF

C_L< 5 pF

Output Enable Time

Output Disable Time

Start-up Time

cycles

C_L< 5 pF

t_START-UPPart start-up time for valid outputs after VDD ramp-up

135MHz, Note 1

Propagation Delay

1.5

2.1

Buffer Additive Phase Jitter, RMS

Output to Output Skew

Device to Device Skew

125MHz, Integration Range: 12kHz-20MHz

Rising edges at VDD/2, Note 2

0.05

500

Rising edges at VDD/2

Notes:

1. With rail to rail input clock

2. Between any 2 outputs with equal loading.

3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.

AUGUST 1, 2016

HIGH-PERFORMANCE 1 TO 5 CLOCK BUFFER

1 2 3 456 7 8...10

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