Datasheet > 5P49EE602NLGI8

5P49EE602NLGI8

更新时间： 2024-02-21 13:18:14

品牌	Logo	应用领域
艾迪悌 - IDT		时钟发生器
页数	文件大小	规格书
25页	438K
描述
VERSACLOCK? LOW POWER CLOCK GENERATOR

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5P49EE602NLGI8 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Not Recommended	零件包装代码：	VFQFPN
包装说明：	HVQCCN, LCC24,.16SQ,20	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.29
JESD-30 代码：	S-XQCC-N24	JESD-609代码：	e3
长度：	4 mm	湿度敏感等级：	3
端子数量：	24	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	120 MHz
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC24,.16SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	1.8 V	主时钟/晶体标称频率：	40 MHz
认证状态：	Not Qualified	座面最大高度：	1 mm
子类别：	Clock Generators	最大供电电压：	1.89 V
最小供电电压：	1.71 V	标称供电电压：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, VIDEO
Base Number Matches：	1

5P49EE602NLGI8 数据手册

IDT5P49EE602

VERSACLOCK^®LOW POWER CLOCK GENERATOR

EEPROM CLOCK GENERATOR

PLL Features and Descriptions

8-bit

VCO

1-bit 11-bit

PLL Block Diagram

Ref-Divider

(D) Values

Feedback

Pre-Divider

(XDIV)

Feedback

Programmable

Spread Spectrum

(M) Values Loop Bandwidth Generation Capability

Values

PLLA

PLLB

PLLC

1 - 255

1 or 4

6 - 2047

Yes

1 or 8 bit

divide

PLLD

1 - 255

1 or 4

6 - 2047

Yes

1.XDIVA or XDIVD=0, A=1. XDIVA or XDIVD=1, A=4.

2.XDIVC =0, A=1. XDIVC=1 turns on 8 bit predivide multiplier, A=FBC2[7:0]. Total feedback divide equals

FBC[10:0] *FBC2[7:0].

Crystal Input (XIN/REF)

Reference Pre-Divider, Reference Divider,

Feedback-Divider and Post-Divider

The crystal oscillators should be fundamental mode quartz

crystals; overtone crystals are not suitable. Crystal

frequency should be specified for parallel resonance with

50 maximum equivalent series resonance.

Each PLL incorporates an 8-bit reference-scaler and a

11-bit feedback divider which allows the user to generate

four unique non-integer-related frequencies. PLLA and

PLLD each have a feedback pre-divider that provides

additional multiplication for kHz reference clock

applications. Each output divider supports 8-bit post-divider.

The following equation governs how the output frequency is

calculated.

Crystal Load Capacitors

The device crystal connections should include pads for

small capacitors from X1 to ground and from X2 to ground.

These capacitors are used to adjust the stray capacitance of

the board to match the nominally required crystal load

capacitance. Because load capacitance can only be

increased in this trimming process, it is important to keep

stray capacitance to a minimum by using very short PCB

traces (and no vias) between the crystal and device. Crystal

capacitors must be connected from each of the pins X1 and

X2 to ground.

A*M

F *

F_OUT

( )

(Eq. 2)

ODIV

Where F is the reference frequency, A is the feedback

pre-divider value, M is the feedback-divider value, D is the

reference divider value, ODIV is the total post-divider value,

and F

is the resulting output frequency. Programming

OUT

The crystal cpacitors are internal to the device and have an

effective value of 8pF.

any of the dividers may cause glitches on the outputs.

IDT™ VERSACLOCK LOW POWER CLOCK GENERATOR

IDT5P49EE602 REV C 061110

1 2 3 456 7 8...25

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