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5M40ZE64I4N

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5M40ZE64I4N 技术参数

8–16

Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices

Document Revision History

f For more information, or to receive BSDL files for IEEE Std. 1149.1-compliant MAX V

devices, refer to the IEEE 1149.1 BSDL Files page on the Altera website.

Document Revision History

Table 8–4 shows the revision history for this chapter.

Table 8–4. Document Revision History

Date

Version

Changes

December 2010

1.0

Initial release.

MAX V Device Handbook

December 2010 Altera Corporation

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型号	品牌	获取价格	描述	数据表
5M40ZE64I5	INTEL	获取价格	Flash PLD, 14ns, PQFP64, 9 X 9 MM, 0.40 MM PITCH, PLASTIC, EQFP-64
5M40ZE64I5N	ALTERA	获取价格	MAX V Device Handbook
5M40ZE64I5N	INTEL	获取价格	Flash PLD, 14ns, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64
5M40ZF64A4N	ALTERA	获取价格	MAX V Device Handbook
5M40ZF64C5N	ALTERA	获取价格	MAX V Device Handbook
5M40ZF64I4N	ALTERA	获取价格	MAX V Device Handbook
5M40ZF64I5N	ALTERA	获取价格	MAX V Device Handbook
5M40ZM64A4N	ALTERA	获取价格	MAX V Device Handbook
5M40ZM64A5N	INTEL	获取价格	Programmable Logic Device
5M40ZM64C4	ALTERA	获取价格	Flash PLD, 7.9ns, PBGA64, 4.50 X 4.50 MM, 0.50 MM PITCH, MBGA-64