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5M40ZE64I4N

更新时间： 2024-02-10 23:14:48

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MAX V Device Handbook

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5M40ZE64I4N 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.59
Base Number Matches：	1

5M40ZE64I4N 数据手册

Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices

8–15

Disabling IEEE Std. 1149.1 BST Circuitry

You can enable the IEEE Std. 1149.1 BST circuitry for MAX V devices after device

powers up. You must enable this circuitry only if you use the BST or ISP features. This

section describes how to disable the IEEE Std. 1149.1 circuitry to ensure that the

circuitry is not inadvertently enabled when it is not required.

Table 8–3 lists the pin connections necessary for disabling JTAG in MAX V devices

that have dedicated IEEE Std. 1149.1 pins.

Table 8–3. Disabling IEEE Std. 1149.1 Circuitry for MAX V Devices

JTAG Pins (1)

TMS

VCC (2)

TCK

TDI

TDO

GND (3)

VCC (2)

Leave Open

Notes to Table 8–3:

(1) There is no software option to disable JTAG in MAX V devices. The JTAG pins are dedicated.

(2) VCC refers to V_CCIOof Bank 1.

(3) The TCKsignal may also be tied high. If TCKis tied high, power-up conditions must ensure that TMSis pulled high

before TCK. Pulling TCKlow avoids this power-up condition.

Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing

When performing boundary-scan testing with IEEE Std. 1149.1 devices, use the

following guidelines:

■

If a pattern (for example, a 10-bit 1010101010pattern) does not shift out of the

instruction register through the TDOpin during the first clock cycle of the SHIFT

state, the proper TAP controller state has not been reached. To solve this problem,

try one of the following procedures:

■

Verify that the TAP controller has reached the SHIFT

IRstate correctly. To

advance the TAP controller to the SHIFT_IRstate, return to the RESETstate and

clock the code 01100on the TMSpin.

■

Check the connections to the VCC, GND, and JTAG pins on the device.

■

Perform a SAMPLE/PRELOADtest cycle before the first EXTESTtest cycle to ensure that

known data is present at the device pins when EXTESTmode is entered. If the OEJ

update register contains a 0, the data in the OUTJupdate register will be driven out.

The state must be known and correct to avoid contention with other devices in the

system.

■

Do not perform EXTESTand SAMPLE/PRELOADtests during ISP. These instructions

are supported before and after ISP but not during ISP.

If problems persist, contact Technical Support.

Boundary-Scan Description Language Support

The BSDL—a subset of VHDL—provides a syntax that allows you to describe the

features of an IEEE Std. 1149.1 BST-capable device that can be tested. Test software

development systems then use the BSDL files for test generation, analysis, failure

diagnostics, and in-system programming.

December 2010 Altera Corporation

MAX V Device Handbook

1...160 161 162163164 165 166

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