Datasheet > 5M2210ZF324C4N

5M2210ZF324C4N

更新时间： 2024-01-24 10:08:29

品牌	Logo	应用领域
阿尔特拉 - ALTERA		时钟 LTE 可编程逻辑
页数	文件大小	规格书
30页	452K
描述
Flash PLD, 9.1ns, 1700-Cell, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, LEAD FREE, FBGA-324

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5M2210ZF324C4N 技术参数

3–30

Chapter 3: DC and Switching Characteristics for MAX V Devices

Document Revision History

Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 2 of 2)

Symbol

Parameter

Min

Max

Unit

t_JSXZ

Notes to Table 3–41:

(1) Minimum clock period specified for 10 pF load on the TDOpin. Larger loads on TDOdegrades the maximum TCKfrequency.

Update register valid output to high impedance

—

(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and

1.5-V LVCMOS operation, the t_JPSUminimum is 6 ns and t_JPCO, t_JPZX, and t_JPXZare maximum values at 35 ns.

Document Revision History

Table 3–42 lists the revision history for this chapter.

Table 3–42. Document Revision History

Date

May 2011

Version

1.2

Changes

Updated Table 3–2, Table 3–15, Table 3–16, and Table 3–33.

Updated Table 3–37, Table 3–38, Table 3–39, and Table 3–40.

Initial release.

January 2011

1.1

December 2010

1.0

MAX V Device Handbook

May 2011 Altera Corporation

1...27 28 2930

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型号	品牌	描述	获取价格	数据表
5M2210ZF324C5N	ALTERA	Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, LEAD FREE, FBGA-324	获取价格
5M2210ZF324I5	ALTERA	Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, FBGA-324	获取价格
5M2210ZF324I5N	ALTERA	Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, LEAD FREE, FBGA-324	获取价格
5M2210ZF64A4N	ALTERA	MAX V Device Handbook	获取价格
5M2210ZF64C5N	ALTERA	MAX V Device Handbook	获取价格
5M2210ZF64I4N	ALTERA	MAX V Device Handbook	获取价格