Datasheet > 5CEFA7F23A7N

5CEFA7F23A7N

更新时间： 2023-01-03 03:33:09

品牌	Logo	应用领域
英特尔 - INTEL		栅
页数	文件大小	规格书
64页	1355K
描述
Field Programmable Gate Array, PBGA484, ROHS COMPLIANT, FBGA-484

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5CEFA7F23A7N 数据手册

Page 60

Glossary

Table 63. Glossary Table (Part 3 of 4)

Letter

Subject

Definitions

Timing Diagram—the period of time during which the data must be valid in order to capture

it correctly. The setup and hold times determine the ideal strobe position within the sampling

window, as shown:

Samplingwindow

(SW)

Bit Time

Sampling Window

(SW)

RSKM

0.5 x TCCS

The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal

values. The AC values indicate the voltage levels at which the receiver must meet its timing

specifications. The DC values indicate the voltage levels at which the final logic state of the

receiver is unambiguously defined. After the receiver input has crossed the AC value, the

receiver changes to the new logic state.

The new logic state is then maintained as long as the input stays beyond the DC threshold.

This approach is intended to provide predictable receiver timing in the presence of input

waveform ringing.

Single-Ended Voltage Referenced I/O Standard

Single-ended

voltage

V_CCIO

referenced I/O

standard

V_OH

V_IH

(

)

V_IH(DC)

V_REF

V_IL(DC)

V_IL(AC

)

V_OL

V_SS

t_C

High-speed receiver/transmitter input and output clock period.

The timing difference between the fastest and slowest output edges, including the t_CO

variation and clock skew, across channels driven by the same PLL. The clock is included in

the TCCS measurement (refer to the Timing Diagram figure under SW in this table).

TCCS (channel-

to-channel-skew)

High-speed I/O block—Duty cycle on high-speed transmitter output clock.

Timing Unit Interval (TUI)

t_DUTY

The timing budget allowed for skew, propagation delays, and the data sampling window.

(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w)

t_FALL

Signal high-to-low transition time (80-20%)

Cycle-to-cycle jitter tolerance on the PLL clock input

Period jitter on the general purpose I/O driven by a PLL

Period jitter on the dedicated clock output driven by a PLL

Signal low-to-high transition time (20–80%)

—

t_INCCJ

t_{OUTPJ_IO}

t_{OUTPJ_DC}

t_RISE

—

Cyclone V Device Datasheet

December 2013 Altera Corporation

1...57 58 596061 62 63 64

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