Datasheet > 5CEFA7F23A7N

5CEFA7F23A7N

更新时间： 2023-01-03 03:33:09

品牌	Logo	应用领域
英特尔 - INTEL		栅
页数	文件大小	规格书
64页	1355K
描述
Field Programmable Gate Array, PBGA484, ROHS COMPLIANT, FBGA-484

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5CEFA7F23A7N 数据手册

Glossary

Page 59

Table 63. Glossary Table (Part 2 of 4)

Letter

Subject

Definitions

High-speed I/O block—Deserialization factor (width of parallel data bus).

JTAG Timing Specifications:

TMS

TDI

t_JCP

JTAG Timing

Specifications

t_JCH

t _JCL

t_JPH

t_JPSU

TCK

TDO

t_JPXZ

t_JPZX

t_JPCO

—

(1)

Diagram of PLL Specifications

CLKOUT Pins

f_{OUT_EXT}

Switchover

CLK

f_IN

f_INPFD

GCLK

RCLK

Counters

C0..C17

f_VCO

VCO

f_OUT

PFD

Core Clock

PLL

Specifications

Delta Sigma

Modulator

Key

External Feedback

Reconfigurable in User Mode

Note:

(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.

—

R_L

Receiver differential input discrete resistor (external to the Cyclone V device).

December 2013 Altera Corporation

Cyclone V Device Datasheet

1...56 57 585960 61 62...64

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5CEFA7F23I7N	ALTERA	Cyclone V Device Datasheet	获取价格
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