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5V9910A-5SO PDF预览

5V9910A-5SO

更新时间： 2024-02-27 05:49:45
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 94K
描述
PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 INCH, SOIC-24

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5V9910A-5SO 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：0.300 INCH, SOIC-24针数：24
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.88系列：5V
输入调节：STANDARDJESD-30 代码：R-PDSO-G24
JESD-609代码：e0长度：15.4178 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.012 A
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：24
实输出次数：8最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP24,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：225电源：3.3 V
Prop。Delay @ Nom-Sup：0.5 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.5 ns座面最大高度：2.6416 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：7.5057 mm
最小 fmax：85 MHzBase Number Matches：1

5V9910A-5SO 数据手册

 浏览型号5V9910A-5SO的Datasheet PDF文件第1页浏览型号5V9910A-5SO的Datasheet PDF文件第3页浏览型号5V9910A-5SO的Datasheet PDF文件第4页浏览型号5V9910A-5SO的Datasheet PDF文件第5页浏览型号5V9910A-5SO的Datasheet PDF文件第6页 
IDT5V9910A  
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE  
RANGES  
PIN CONFIGURATION  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol  
Description  
Supply Voltage to Ground  
DC Input Voltage  
Max  
–0.5 to +7  
–0.5 to VCC+0.5  
–0.5 to +5.5  
530  
Unit  
V
VI  
V
1
GND  
TEST  
NC  
REF  
VCCQ  
FS  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
REF Input Voltage  
V
2
Maximum Power Dissipation (TA = 85°C)  
Storage Temperature  
mW  
°C  
3
TSTG  
–65 to +150  
NC  
4
GND/sOE  
VCCN  
Q7  
NOTE:  
5
VCCQ/PE  
VCCN  
Q0  
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause per-  
manent damage to the device. These are stress ratings only, and functional operation of  
the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute-maximum-rated condi-  
tions for extended periods may affect device reliability.  
6
7
Q6  
Q1  
8
GND  
Q5  
GND  
Q2  
9
10  
11  
12  
Q4  
Q3  
VCCN  
FB  
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)  
VCCN  
Parameter Description  
Typ.  
Max.  
Unit  
CIN  
Input Capacitance  
5
7
pF  
NOTE:  
SOIC  
1. Capacitance applies to all inputs except TEST and FS. It is characterized but not produc-  
tion tested.  
TOP VIEW  
PIN DESCRIPTION  
Pin Name  
REF  
Type  
IN  
Description  
Reference Clock Input  
Feedback Input  
FB  
IN  
TEST (1)  
GND/ sOE(1)  
IN  
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.  
IN  
Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as  
the feedback signal to maintain phase lock. Set GND/sOELOW for normal operation.  
VCCQ/PE  
FS(2)  
IN  
IN  
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of  
the reference clock.  
Frequency range select:  
FS = GND: 15 to 35MHz  
FS = MID (or open): 25 to 60MHz  
FS = VCC: 40 to 85MHz  
Q0 - Q7  
VCCN  
VCCQ  
GND  
OUT  
PWR  
PWR  
PWR  
Eight clock output  
Power supply for output buffers  
Power supply for phase locked loop and other internal circuitry  
Ground  
NOTES:  
1. When TEST = MID and GND/sOE= HIGH, PLL remains active.  
2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional lock time  
before all data sheet limits are achieved.  
2
123456

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