UT1553 BCRTM
p Register-oriented architecture to enhance
FEATURES
programmability
p Comprehensive MIL-STD-1553 dual-redundant Bus
Controller (BC) and Remote Terminal (RT) and
Monitor (M) functions
p DMA memory interface with 64K addressability
p Internal self-test
p MIL-STD-1773 compatible
p Multiple message processing capability in BC
p TimetaggingandmessagelogginginRTandMmodes
p Radiation-hardened option available for 84-lead
flatpack package only
p RemoteterminaloperationsinASD/ENASD-certified
(SEAFAC)
p Automatic polling and intermessage delay in
p Availablein84-pinpingridarray, 84-leadflatpack, 84-
BC mode
lead leadless chip-carrier
p Programmable interrupt scheme and internally
p Standard Microcircuit Drawing 5962-89577 available
generated interrupt history list
- QML Q and V compliant
REGISTERS
CONTROL
STATUS
HIGH-PRIORITY
STD PRIORITY LEVEL
STD PRIORITY PULSE
MASTER
RESET
CURRENT BC (or M) BLOCK/
12MHz
RT DESCRIPTOR SPACE
POLLING COMPARE
BUILT-IN-TEST WORD
CURRENT COMMAND
INTERRUPT
HANDLER
CLOCK &
RESET
LOGIC
INTERRUPT LOG
LIST POINTER
BC PROTOCOL
&
MESSAGE
HANDLER
HIGH-PRIORITY
INTERRUPT ENABLE
PARALLEL-
TO-SERIAL
CONVER-
SION
1553
DUAL
DATA
CHANNEL
A
HIGH-PRIORITY
INTERRUPT STATUS
CHANNEL
ENCODER/
DECODER
MODULE
BUS
TRANSFER
LOGIC
16
16
STANDARD INTERRUPT
ENABLE
1553
SERIAL-TO-
PARALLEL
CONVER-
DATA
CHANNEL
B
16
RT ADDRESS
SION
RT/MONITOR
PROTOCOL &
MESSAGE
BUILT-IN-TEST
START COMMAND
16
HANDLER
BUILT-
IN-
TEST
RESET COMMAND
16
RT TIMER
RESET COMMAND
TIMERON
ADDRESS
GENERATOR
16
TIMEOUT
DMA/CPU
CONTROL
MONITOR ADDRESS
CONTROL
MONITOR ADDRESS
SELECT (0-15)
DMA ARBITRATION
ADDRESS
REGISTER CONTROL
DUAL-PORT MEMORY CONTROL
MONITOR ADDRESS
SELECT (16-31)
16
16
Figure 1. BCRTM Block Diagram
DATA
BCRTM-1