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5962R0724903QXC PDF预览

5962R0724903QXC

更新时间： 2024-01-11 19:22:28
品牌 Logo 应用领域
英特矽尔 - INTERSIL 开关控制器
页数 文件大小 规格书
11页 648K
描述
Radiation Hardened, High Performance IndustryStandard Single-Ended Current Mode PWM Controller

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5962R0724903QXC 技术参数

是否Rohs认证：符合生命周期：Transferred
零件包装代码：DFP包装说明：DFP, FL8,.25
针数：8Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.18Is Samacsys：N
模拟集成电路 - 其他类型：SWITCHING CONTROLLER控制模式：CURRENT-MODE
控制技术：PULSE WIDTH MODULATION最大输入电压：13.2 V
最小输入电压：9 VJESD-30 代码：R-CDFP-F8
JESD-609代码：e4长度：6.485 mm
功能数量：1端子数量：8
最高工作温度：125 °C最低工作温度：-55 °C
最大输出电流：1 A封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DFP封装等效代码：FL8,.25
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
筛选级别：MIL-PRF-38535 Class V座面最大高度：2.92 mm
子类别：Switching Regulator or Controllers表面贴装：YES
切换器配置：SINGLE最大切换频率：1000 kHz
温度等级：MILITARY端子面层：Gold (Au)
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
总剂量：100k Rad(Si) V宽度：6.475 mm
Base Number Matches：1

5962R0724903QXC 数据手册

 浏览型号5962R0724903QXC的Datasheet PDF文件第4页浏览型号5962R0724903QXC的Datasheet PDF文件第5页浏览型号5962R0724903QXC的Datasheet PDF文件第6页浏览型号5962R0724903QXC的Datasheet PDF文件第8页浏览型号5962R0724903QXC的Datasheet PDF文件第9页浏览型号5962R0724903QXC的Datasheet PDF文件第10页 
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH  
the average output current can be calculated from  
Equation 5:  
Gate Drive  
The ISL7884xASRH is capable of sourcing and sinking 1A  
peak current. To limit the peak current through the IC, an  
optional external resistor may be placed between the  
totem-pole output of the IC (OUT pin) and the gate of  
the MOSFET. This small series resistor also damps any  
oscillations caused by the resonant tank of the parasitic  
inductances in the traces of the board and the FET’s input  
capacitance. TID environment of >50krads requires the  
use of a bleeder resistor of 10k from OUT pin to GND.  
(EQ. 5)  
I
= Qg × f  
OUT  
To optimize noise immunity, bypass V  
to GND with a  
and GND pins as  
DD  
ceramic capacitor as close to the V  
possible.  
DD  
V
- The 5.00V reference voltage output. +1.0/-1.5%  
REF  
tolerance over line, load and operating temperature. The  
recommended bypass to GND cap is in the range 0.1µF  
to 0.22µF. A typical value of 0.15µF can be used.  
Slope Compensation  
For applications where the maximum duty cycle is less  
than 50%, slope compensation may be used to improve  
noise immunity, particularly at lighter loads. The amount  
of slope compensation required for noise immunity is  
determined empirically, but is generally about 10% of the  
full scale current feedback signal. For applications where  
the duty cycle is greater than 50%, slope compensation  
is required to prevent instability.  
Functional Description  
Features  
The ISL7884xASRH current mode PWM makes an ideal  
choice for low-cost flyback and forward topology  
applications. With its greatly improved performance over  
industry standard parts, it is the obvious choice for new  
designs or existing designs which require updating.  
Slope compensation may be accomplished by summing  
an external ramp with the current feedback signal or by  
subtracting the external ramp from the voltage feedback  
error signal. Adding the external ramp to the current  
feedback signal is the more popular method.  
Oscillator  
The ISL7884xASRH has a sawtooth oscillator with a  
programmable frequency range to 2MHz, which can be  
programmed with a resistor from V  
GND on the RTCT pin. (Please refer to Figure 4 for the  
and a capacitor to  
REF  
From the small signal current-mode model [1] it can be  
shown that the naturally-sampled modulator gain, Fm,  
without slope compensation is calculated in Equation 6:  
resistor and capacitance required for a given frequency).  
Soft-Start Operation  
1
Soft-start must be implemented externally. One method,  
illustrated below, clamps the voltage on COMP.  
-------------------  
Fm =  
(EQ. 6)  
SnTsw  
where Sn is the slope of the sawtooth signal and tsw is  
the duration of the half-cycle. When an external ramp is  
added, the modulator gain becomes Equation 7:  
V
REF  
1
1
(EQ. 7)  
------------------------------------  
-------------------------  
Fm =  
=
D1  
C1  
R1  
(Sn + Se)tsw  
m Sntsw  
c
COMP  
GND  
Q1  
where Se is slope of the external ramp and becomes  
Equation 8:  
Se  
Sn  
-------  
m
= 1 +  
(EQ. 8)  
c
The criteria for determining the correct amount of  
external ramp can be determined by appropriately  
FIGURE 5. SOFT-START  
setting the damping factor of the double-pole located at  
the switching frequency. The double-pole will be critically  
damped if the Q-factor is set to 1, over-damped for Q <  
1, and under-damped for Q > 1. An under-damped  
condition may result in current loop instability.  
The COMP pin is clamped to the voltage on capacitor C  
1
plus a base-emitter junction by transistor Q . C is  
1
1
charged from V  
through resistor R and the base  
REF  
1
current of Q . At power-up C is fully discharged, COMP  
1
1
is at ~0.7V, and the duty cycle is zero. As C1 charges,  
the voltage on COMP increases, and the duty cycle  
1
(EQ. 9)  
-------------------------------------------------  
Q =  
π(m (1 – D) – 0.5)  
c
increases in proportion to the voltage on C . When COMP  
1
reaches the steady state operating point, the control loop  
takes over and soft start is complete. C continues to  
1
charge up to V  
and no longer affects COMP. During  
REF  
power down, diode D1 quickly discharges C1 so that the  
soft start circuit is properly initialized prior to the next  
power on sequence.  
FN6991.0  
December 21, 2009  
7
1...4567891011

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