Datasheet > 5962F0620202

5962F0620202

更新时间： 2024-01-26 23:25:02

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		接口集成电路
页数	文件大小	规格书
17页	430K
描述
LINE RECEIVER

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5962F0620202 技术参数

生命周期：	Active	包装说明：	HDFP,
Reach Compliance Code：	unknown	风险等级：	5.68
差分输出：	YES	驱动器位数：	2
输入特性：	DIFFERENTIAL	接口集成电路类型：	LINE TRANSCEIVER
JESD-30 代码：	R-XDFP-F18	长度：	11.81 mm
功能数量：	2	端子数量：	18
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	UNSPECIFIED	封装代码：	HDFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, HEAT SINK/SLUG
最大接收延迟：	2.5 ns	接收器位数：	2
筛选级别：	MIL-PRF-38535 Class V	座面最大高度：	2.74 mm
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
温度等级：	MILITARY	端子形式：	FLAT
端子节距：	1.27 mm	端子位置：	DUAL
总剂量：	300k Rad(Si) V	最大传输延迟：	1.5 ns
宽度：	7.11 mm	Base Number Matches：	1

5962F0620202 数据手册

Electrical characteristics

RHFLVDSR2D2

Table 7. Electrical characteristics (continued)

Parameter Test conditions Min.

Symbol

Typ.

Max.

Unit

t_SK1

t_SK2

Channel-to-channel skew⁽²⁾

Chip-to-chip skew⁽³⁾⁽⁴⁾

Differential skew⁽⁵⁾

0.25

0.7

V_ID= 200 mVp-p

Load: refer to Figure 3

t_SKD

0.3

(t_PHLD-t_PLHD

)

t _r

t _f

Output signal rise time

Output signal fall time

0.9

Load: refer to Figure 3

Propagation delay time, low

level to high impedance output

t_PLZ

t_PHZ

t_PZH

t_PZL

3.8

Propagation delay time, high

level to high impedance output

Load: refer to Figure 4

Propagation delay time, high

impedance to high level output

Propagation delay time, high

impedance to low level output

t_D1

t_D2

Fail-safe to active time

Active to fail-safe time

µs

1. All pins except pin under test and V_CCare floating

2. t_SK1is the maximum delay time difference between all outputs of the same device (measured with all inputs connected

together).

3. t_SK2is the maximum delay time difference between outputs of all devices when they operate with the same supply voltage,

at the same temperature.

4. Guaranteed by design

5. t_SKDis the maximum delay time difference between t_PHLDand t_PLHD, see Figure 3.

6. Guaranteed by characterization on bench.

Cold sparing

The RHFLVDSR2D2 features a cold spare input and output buffer. In high reliability

applications, cold sparing enables a redundant device to be tied to the data bus with its

power supply at 0 V (V = GND) without affecting the bus signals or injecting current from

the I/Os to the power supplies. Cold sparing also allows redundant devices to be kept

powered off so that they can be switched on only when required. This has no impact on the

application. Cold sparing is achieved by implementing a high impedance between the I/Os

and V . ESD protection is ensured through a non-conventional dedicated structure.

Fail-safe

In many applications, inputs need a fail-safe function to avoid an uncertain output state

when the inputs are not connected properly. For the drivers: in case of an LVDS input short

circuit or floating inputs, the TTL outputs remain in stable logic-high state.

8/17

DocID025372 Rev 2

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